View HD40A46612_5060918.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

hd404669 series low-voltage as microcomputers with on-chip dtmf generation circuit ade-202-083b rev. 3.0 sept. 1999 description the hd404669 series microcomputers incorporate a dtmf generation circuit, two comparators, and a serial interface on chip. they also provide input and output pins with large current handling capacities. thus they are 4-bit single-chip microcomputers that are optimal for use in multifunction telephones, cordless telephones, and other communications equipment. hd404669 series microcomputers have a 32.768 khz sub-oscillator for realtime clock use, providing a time counting facility, and a variety of power supply modes to reduce current drain. the hd407a4669 is a ztat microcomputer with on-chip prom that drastically shortens development time and ensures a smooth transition from debugging to mass production. (the prom programming specifications are the same as for the 27256 type.) ztat: zero turn-around time ztat is a trademark of hitachi, ltd. features 1,152-digit 4-bit ram i/o pins: 47 ? high-current i/o pins (source: 10 ma max.): 4 ? high-current i/o pins (sink: 15 ma max.): 5 timer counters: 3 input capture: one 8-bit channel timer outputs: 2 (with pwm output capability) event input: 1 (edge-programmable) clock synchronous 8-bit serial interface: 1 dtmf generation circuit comparator: 2 channels system clock oscillator ceramic oscillator, crystal oscillator, or external clock operation possible
hd404669 series 2 subsystem clock oscillator 32.768 khz crystal oscillator for realtime clock use interrupts ? external: 5 (including 3 edge-programmable) ? internal: 4 subroutine stack: max. 16 levels including interrupts low-power modes: 4 system clock division software switching (1/4, 1/8, 1/16, 1/32) instruction execution time min. 1 m s (f osc = 4 mhz, 1/4 clock division) min. 0.5 m s (f osc = 8 mhz, 1/4 clock division) operating voltage 1.8 v to 5.5 v 2.2 v to 5.5 v (ztat) ordering information type product name model name rom (words) ram (digits) package mask rom (standard version) hd404668 hd404668h 8,192 1,152 64-pin plastic qfp (fp-64a) hd4046612 hd4046612h 12,288 hd404669 hd404669h 16,384 hcd404669 hcd404669 16,384 chip * 1 * 2 mask rom (high-speed version) hd40a4668 hd40a4668h 8,192 64-pin plastic qfp (fp-64a) HD40A46612 HD40A46612h 12,288 hd40a4669 hd40a4669h 16,384 ztat (high-speed version) hd407a4669 hd407a4669h 16,384 note: 1. ztat chip shipment is not supported. 2. the specifications of shipped chips differ from those of the package product. please contact our sales staff for details. cautions about operation the mask rom and ztat versions have been confirmed as fully meeting the reference values for electrical characteristics shown in this data sheet. however, actual performance figures, operating margins, noise margins, and other properties may vary due to differences in the manufacturing process, internal
hd404669 series 3 wiring patterns, etc. users are therefore requested to confirm the operation of individual products by conducting evaluation tests under conditions equivalent to those in the actual application system. list of functions standard version hd404668 hd4046612 hd404669 hcd404669 product name high- speed version hd40a4668 HD40A46612 hd40a4669 hd407a4669 rom (words) 8,192 12,288 16,384 16,384 16,384prom ram (digits) 1,152 i/o 52 (max) large-current i/o pins 4 ( source 10ma max), 5 (sink 15 ma max) timer / counter 3 input capture 8 bit 1 timer output 2 (pwm output possible) event input 1 (edge selection possible) serial interface 1 (8-bit clock syncronous) dtmf generation circuit available comparator 2 interrupt external 5 (edge selection possible for 3) internal 4 low-power dissipation mode 4 stop mode available watch /mode available standby mode available subactive mode available main oscillator ceramic oscillation 400 khz, 800 khz, 2 mhz, 3.58 mhz, 4 mhz, 7.16 mhz * , 8 mhz * crystal oscillation 400 khz, 800 khz, 2 mhz, 3.58 mhz, 4 mhz, 7.16 mhz * , 8 mhz * sub oscillator crystal oscillation 32.768 khz minimum instruction execution time standard version 1 m s (f osc = 4 mhz, 1/4 frequency division) high-speed version 0.5 m s (f osc = 8 mhz, 1/4 frequency division) operating voltage (v) 1.8 to 5.5 1.8 to 5.5 2.2 to 5.5 package 64-pin plastic qfp (fp-64a) chip 64-pin plastic qfp (fp-64a) guaranteed operation temperature (?c) ?0 to +75 +75 c ?0 to +75 note: * applies to high-speed versions (hd40a4668, HD40A46612, hd40a4669, hd407a4669).
hd404669 series 4 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 r8 0 r7 3 r7 2 r7 1 r7 0 r6 3 r6 2 r6 1 r6 0 r4 3 /so 1 r4 2 /si 1 r4 1 / sck 1 r4 0 /evnd r3 1 /toc r3 2 /tod r3 3 re 0 /vc ref test osc 1 osc 2 reset x1 x2 gnd d 5 d 9 d 10 d 3 d 4 d 1 d 2 d 0 rd 1 /comp 1 rd 0 /comp 0 vt ref toner tonec v cc sel ra 1 ra 0 r9 3 r9 2 r9 1 r9 0 r8 3 r8 2 r8 1 d 11 r0 1 /int 2 r0 2 /int 3 r0 3 /int 4 r2 1 r2 2 r2 3 r3 0 fp-64a top view d 12 / stopc d 13 / int 0 r0 0 r1 3 r2 0 r1 0 r1 1 r1 2 / int 1
hd404669 series 5 pad arrangement hcd404669 64 type code type code: hd404669 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
hd404669 series 6 bonding pad coordinates hcd404669 type code chip size (x y): 4.34 4.01 (mm) coordinates: pad center home point position: chip center pad size (x y): 90 90 ( m) chip thickness: 400 ( m) y x chip center (x=0, y=0) pad pad coordinates pad pad coordinates pad pad coordinates pad pad coordinates no. name x y no. name x y no. name x y no. name x y 1 re0 ?983 1444 17 d11 ?607 ?819 33 r33 1983 ?444 49 r81 1587 1819 2 testn ?983 1252 18 d12 ?394 ?819 34 r32 1983 ?252 50 r82 1374 1819 3 osc1 ?983 1062 19 d13 ?181 ?819 35 r31 1983 ?060 51 r83 1161 1819 4 osc2 ?983 871 20 r00 ?68 ?819 36 r40 1983 ?67 52 r90 948 1819 5 reset ?983 657 21 r01 ?55 ?819 37 r41 1983 ?75 53 r91 735 1819 6 x1 ?983 466 22 r02 ?41 ?819 38 r42 1983 ?83 54 r92 522 1819 7 x2 ?983 275 23 r03 ?29 ?819 39 r43 1983 ?91 55 r93 309 1819 8 gnd ?983 84 24 r10 ?17 ?819 40 r60 1983 ?9 56 ra0 93 1819 9 d0 ?983 ?08 25 r11 96 ?819 41 r61 1983 93 57 ra1 ?77 1819 10 d1 ?983 ?99 26 r12 309 ?819 42 r62 1983 285 58 sel ?29 1819 11 d2 ?983 ?90 27 r13 522 ?819 43 r63 1983 478 59 v cc ?42 1819 12 d3 ?983 ?80 28 r20 735 ?819 44 r70 1983 670 60 tonec ?55 1819 13 d4 ?983 ?71 29 r21 948 ?819 45 r71 1983 862 61 toner ?68 1819 14 d5 ?983 ?062 30 r22 1161 ?819 46 r72 1983 1054 62 vtref ?181 1819 15 d9 ?983 ?253 31 r23 1374 ?819 47 r73 1983 1246 63 rd0 ?394 1819 16 d10 ?983 ?444 32 r30 1587 ?819 48 r80 1983 1444 64 rd1 ?607 1819
hd404669 series 7 pin description pin number item symbol fp-64a, chip i/o function power v cc 59 applies power voltage supply gnd 8 connected to ground test test 2 i used for factory testing only: connect this pin to v cc reset reset 5 i resets the mcu oscillator osc 1 3 i input/output pins for the internal oscillator circuit: connect them to a ceramic oscillator ,crystal oscillator or connect osc 1 to an external oscillator circuit osc 2 4o x1 6 i used for a 32.768-khz crystal for clock purposes. if not to be used, fix the x1 pin to v cc and leave the x2 pin open. x2 7 o port d 0 ? 5 , d 9 ? 11 9-17 i/o input/output pins addressed by individual bits; d 0 to d 3 are source high-current input/output pins. a maximum 10 ma current can be supplied to each pin. d 4 , d 5 , and d 9 to d 11 are sink high-current input/output pins. a maximum 15 ma current can be supplied to each pin. d 12 , d 13 18, 19 i input pins addressable by individual bits r0 0 ?4 3, r6 0 ?a 1 20?7 i/o input/output pins addressable in 4-bit units rd 0 , rd 1, re 0 63, 64, 1 i input pins addressable in 4-bit units interrupt int 0 , int 1 , int 2 ?nt 4 19-23 i input pins for external interrupts stop clear stopc 18 i input pin for transition from stop mode to active mode serial sck 1 37 i/o serial interface clock input/output pin interface si 1 38 i serial interface receive data input pin so 1 39 o serial interface transmit data output pin timer toc, tod 35, 34 o timer output pins evnd 36 i event input pin dtmf toner 61 o output pin for dtmf row signals tonec 60 o output pin for dtmf column signals vt ref 62 reference voltage pin for dtmf signals. voltage conditions are: v cc 3 vt ref 3 gnd
hd404669 series 8 pin number item symbol fp-64a, chip i/o function voltage comparator comp 0 , comp 1 63, 64 i comparator analog input pins. vc ref 1 analog input pin threshold voltage reference level power supply pin. frequency division ratio selection sel 58 i pin that selects the system clock division ratio immediately after a reset and when returning from stop mode to active mode. connect to vcc voltage to select division-by-4, or to gnd potential to select division-by-32.
hd404669 series 9 block diagram : data bus reset test stopc osc 1 osc 2 x1 x2 v cc gnd sel hmcs400 cpu rom ram 8-bit timer a (free-running timer) 8-bit timer c d 0 d 1 d 2 d 3 d 4 d 5 d 9 d 10 d 11 d 12 d 13 r4 0 r4 1 r4 2 r4 3 r0 port r0 0 r0 1 r0 2 r0 3 r1 0 r1 1 r1 2 r1 3 r2 0 r2 1 r2 2 r2 3 r3 0 r3 1 r3 2 r3 3 r6 0 r6 1 r6 2 r6 3 toc vc ref comp 0 comp 1 comparator external interrupt control circuit int 0 int 1 int 2 int 3 int 4 r7 0 r7 1 r7 2 r7 3 8-bit timer d evnd tod synchronous 8-bit serial interface sck 1 si 1 so 1 ra 0 ra 1 rd 0 rd 1 re 0 : signal line r9 0 r9 1 r9 2 r9 3 r8 0 r8 1 r8 2 r8 3 dtmf generation circuit vt ref toner tonec d port r1 port r2 port r3 port r4 port r6 port r7 port r8 port r9 port ra port rd port re port
hd404669 series 10 memory map rom memory map the rom memory map is shown in figure 1 and described below. vector addresses (16 words) zero page subroutine area (64 words) pattern area (4,096 words) hd404668/hd40a4668 program area (8,192 word) $000f $0fff $1000 $3fff $0010 $003f $0040 $0000 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f rom address jmpl instruction (jump to reset, stop mode clearance routine) jmpl instruction (jump to int 0 interrupt handling routine) jmpl instruction (jump to int 1 interrupt handling routine) rom address hd4046612/HD40A46612 program area (12,288 words) hd404669/hd40a4669/ hcd404669/hd407a4669 program area (16,384 words) $1fff $2000 $2fff $3000 jmpl instruction (jump to timer a interrupt handling routine) jmpl instruction (jump to int 2 interrupt handling routine) jmpl instruction (jump to timer c, int 3 interrupt handling routine) jmpl instruction (jump to timer d, int 4 interrupt handling routine) jmpl instruction (jump to serial 1 routine) figure 1 rom memory map vector address area ($0000?000f): reserved for jmpl instructions that branch to the start addresses of the reset and interrupt routines. after mcu reset or an interrupt, program execution continues from the vector address. zero-page subroutine area ($0000?003f): reserved for subroutines. the program branches to a subroutine in this area in response to the cal instruction. pattern area ($0000?0fff): contains rom data that can be referenced with the p instruction. program area ($0000?1fff: hd404668, hd40a4668; $0000?2fff: hd4046612, HD40A46612; $0000?3fff: hd404669, hd40a4669, hd407a4669, hcd404669): used for program coding.
hd404669 series 11 ram memory map the mcu contains a ram area consisting of a memory register area, a data area, and a stack area. in addition, an interrupt control bits area, special function register area, and register flag area are mapped onto the same ram memory space. the ram memory map is shown in figure 2 and described below. ram-mapped register area ($000?03f): interrupt control bits area ($000?003) this area is used for interrupt control bits (figure 3). these bits can be accessed only by ram bit manipulation instructions (sem/semd, rem/remd, and tm/tmd). however, note that not all the instructions can be used for each bit. limitations on using the instructions are shown in figure 4. special function register area ($004?01f, $024?03f) this area is used as mode registers and data registers for external interrupts, serial interface, timers, dtmf, comparator, and as data control registers for i/o ports. the structure is shown in figures 2 and 5. these registers can be classified into three types: write-only (w), read-only (r), and read/write (r/w). ram bit manipulation instructions cannot be used for these registers. register flag area ($020?023) this area is used for the dton, wdon, and other register flags and interrupt control bits (figure 3). these bits can be accessed only by ram bit manipulation instructions (sem/semd, rem/remd, and tm/tmd). however, note that not all the instructions can be used for each bit. limitations on using the instructions are shown in figure 4.
hd404669 series 12 $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00a $00b $00c $00d $00e $00f $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01a $01b $01c $01d $01e $01f $020 $021 $022 $023 $024 $025 $026 $027 $028 $029 $02a $02b $02c $02d $02e $02f $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 $03a $03b $03c $03d $03e $03f port mode register a serial mode register 1a serial data register 1l serial data register 1u timer mode register a miscellaneous register timer mode register c1 timer c timer mode register d1 timer d timer mode register c2 timer mode register d2 compare data register compare enable register tone generator mode register tone generator control register system clock select register 1 system clock select register 2 data control register d 0 to d 3 data control register d 4 to d 5 data control register d 9 to d 11 data control register r0 data control register r1 data control register r2 data control register r3 data control register r4 data control register r6 data control register r7 data control register r8 data control register r9 data control register ra v register interrupt control bit area register flag area not used (pmra) (sm1a) (sr1l) (sr1u) (tma) (mis) (tmc1) (trcl/twcl) (trcu/twcu) (tmd1) (trdl/twdl) (trdu/twdu) (tmc2) (tmd2) (cdr) (cer) (tgm) (tgc) (pmrb) (pmrc) (esr1) (esr2) (sm1b) (ssr1) (ssr2) (dcd0) (dcd1) (dcd2) (dcr0) (dcr1) (dcr2) (dcr3) (dcr4) (dcr6) (dcr7) (dcr8) (dcr9) (dcra) w w r/w r/w w w w r/w r/w w r/w r/w r/w r/w r w w w w w w w w w w w w w w w w w w w w w w w (v) r/w (twcl) (twcu) (twdl) (twdu) w w w w r r r r $000 $260 $3c0 $3ff ram-mapped register area memory registers (16 digits) data (464 digits x 2) v = 0 (bank = 0) v = 1 (bank = 1) data (144 digits) stack area (64 digits) r w r/w : read only : write only : read/write * 1 not used ram address ram address $040 $050 not used $2f0 $090 port mode register b port mode register c detection edge select register 1 detection edge select register 2 serial mode register 1b $00e $00f $011 $012 timer read register cl timer read register cu timer read register dl timer read register du (trcl) (trcu) (trdl) (trdu) timer write register cl timer write register cu timer write register dl timer write register du $090 $25f note : * 1. there are two data areas, v = 0 (bank 0) and v = 1 (bank 1) data (464 digits) v = 0 (bank = 0) data (464 digits) v = 1 (bank = 1) * 2. two registers are mapped onto the same address ($00e, $00f, $011, $012) * 2 not used not used not used not used not used not used not used * 2 figure 2 ram memory map
hd404669 series 13 if im ie sp : interrupt request flag : interrupt mask : interrupt enable flag : stack pointer interrupt control bits area register flag area ram address $000 $001 $002 $003 im0 ( int 0 interrupt mask) if0 ( int 0 interrupt request flag) rsp (reset stack pointer) ie (interrupt enable flag) imta (timer a interrupt mask) ifta (timer a interrupt request flag) im1 ( int 1 interrupt mask) if1 ( int 1 interrupt request flag) imtc (timer c interrupt mask) iftc (timer c interrupt request flag) not used not used ims1 (serial 1 interrupt mask) ifs1 (serial 1 interrupt request flag) imtd (timer d interrupt mask) iftd (timer d interrupt request flag) bit 3 bit 2 bit 1 bit 0 ram address $020 $021 $022 $023 bit 3 bit 2 bit 1 bit 0 dton (dton flag) not used not used wdon (watchdog on flag) lson (low speed on flag) rame (ram enable flag) icef (input capture error flag) icsf (input capture status flag) im3 (int 3 interrupt mask) if3 (int 3 interrupt request flag) im2 (int 2 interrupt mask) if2 (int 2 interrupt request flag) not used not used im4 (int 4 interrupt mask) if4 (int 4 interrupt request flag) figure 3 configuration of interrupt control bits and register flag areas
hd404669 series 14 ie im lson if icsf icef rame rsp wdon not used dton sem/semd allowed allowed not executed in active mode used in subactive mode allowed allowed not executed not executed not executed allowed allowed not executed allowed not executed allowed inhibited inhibited allowed inhibited rem/remd tm/tmd bits in the interrupt control bits area and register flag area can be set and reset by the sem or semd instruction and the rem or remd instruction, and tested by the tm or tmd instruction. they are not affected by any other instructions. the following restrictions apply to individual bits. note: wdon is reset by mcu reset or by stopc enable for stop mode cancellation. dton is always reset in active mode. if the tm or tmd instruction is executed for the inhibited bits or non-existing bits, the value in st becomes invalid. figure 4 usage limitations of ram bit manipulation instructions
hd404669 series 15 bit 3 bit 2 bit 1 $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00a $00b $00c $00d $00e $00f $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01a $01b $01c $01d $01e $01f $020 $021 $022 $023 $024 $025 $026 $027 $028 $029 $02a $02b $02c $02d $02e $02f $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 $03a $03b $03c $03d $03e $03f pmra sm1a sr1l sr1u tma mis tmc1 trcl/twcl trcu/twcu tmd1 trdl/twdl trdu/twdu tmc2 tmd2 cdr cer tgm tgc pmrb pmrc esr1 esr2 sm1b ssr1 ssr2 dcd0 dcd1 dcd2 dcr0 dcr1 dcr2 dcr3 dcr4 dcr6 dcr7 dcr8 dcr9 dcra v interrupt control bits area r4 2 / si 1 r4 3 / so 1 r4 1 / sck 1 serial data register 1 (lower) serial data register 1 (upper) serial transfer clock speed selection 1 clock source setting (timer a) mos pull-up/pull-down control r4 3 /so 1 pmos control timer c register (lower) timer c register (upper) bit 0 port r0 3 dcr port r1 3 dcr port r2 3 dcr port r3 3 dcr port r0 2 dcr port r1 2 dcr port r2 2 dcr port r3 2 dcr port r0 1 dcr port r1 1 dcr port r2 1 dcr port r3 1 dcr port r0 0 dcr port r1 0 dcr port r2 0 dcr port r3 0 dcr clock source setting (timer c) timer a/time base interrupt frame period selection reload on/off reload on/off clock source setting (timer d) timer d register (lower) timer d register (upper) input capture selection timer c output mode setting timer d output mode setting comp 0 comparison result comp 1 comparison result register flag area r0 3 /int 4 d 13 / int 0 r0 2 /int 3 d 12 / stopc r0 1 /int 2 r4 0 /evnd r0 0 / int 1 int 2 detection edge selection int 3 detection edge selection int 4 detection edge selection evnd detection edge selection * 2 * 1 so1 idle high/low setting serial clock selection port d 3 dcr port d 11 dcr port d 2 dcr port d 10 dcr port d 1 dcr port d 5 dcr port d 0 dcr port d 4 dcr port d 9 dcr port r4 3 dcr port r6 3 dcr port r7 3 dcr port r4 2 dcr port r6 2 dcr port r7 2 dcr port r4 1 dcr port r6 1 dcr port r7 1 dcr port r4 0 dcr port r6 0 dcr port r7 0 dcr port r8 3 dcr port r8 2 dcr port r8 1 dcr port r8 0 dcr port r9 3 dcr port r9 2 dcr port r9 1 dcr port r9 0 dcr port ra 1 dcr port ra 0 dcr bank setting : not used * 1: 32khz oscillation stop setting * 2: 32khz fre q uenc y division ratio switchin g toner output frequency tonec output frequency tonec output comparator operation selection comparator selection toner output dtmf enable dtmf speed setting osc frequency division ratio switching dtmf speed setting figure 5 special function register area
hd404669 series 16 memory register (mr) area ($040?04f): consisting of 16 addresses, this area (mr0?r15) can be accessed by register-register instructions (lamr and xmra). the structure is shown in figure 6. (b) stack area (a) memory registers pc 13 to pc 0 st ca : program counter : status flag : carry flag $3c0 $3ff level 16 level 15 level 14 level 13 level 12 level 11 level 10 level 9 level 8 level 7 level 6 level 5 level 4 level 3 level 2 level 1 pc 11 pc 7 pc 4 pc 0 pc 12 pc 8 pc 5 pc 1 pc 13 pc 9 pc 6 pc 2 st pc 10 ca pc 3 bit 3 bit 2 bit 1 bit 0 $3fc $3fd $3fe $3ff ram address mr mr mr mr mr mr mr mr mr mr mr mr mr mr mr mr (0) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) $040 $041 $042 $043 $044 $045 $046 $047 $048 $049 $04a $04b $04c $04d $04e $04f figure 6 configuration of memory registers and stack area, and stack position
hd404669 series 17 data area ($090?2ef): 464 digits from $090 to $25f have two banks, which can be selected by setting the bank register (v: $03f). before accessing this area, set the bank register to the required value (figure 7). the area from $026 to $2ef is accessed without setting the bank register. bit initial value read/write bit name 3 not used 2 not used 0 0 r/w v0 1 not used v0 0 1 bank area selection bank 0 is selected bank 1 is selected note: after reset, the value in the bank register is 0, and therefore bank 0 is selected. bank register (v: $03f) figure 7 bank register (v) stack area ($3c0?3ff): used for saving the contents of the program counter (pc), status flag (st), and carry flag (ca) at subroutine call (cal or call instruction) and for interrupts. this area can be used as a 16-level nesting subroutine stack in which one level requires four digits. the data to be saved and the save conditions are shown in figure 6. the program counter is restored by either the rtn or rtni instruction, but the status and carry flags can only be restored by the rtni instruction. any unused space in this area is used for data storage.
hd404669 series 18 functional description registers and flags the mcu has nine registers and two flags for cpu operations. they are shown in figure 8 and described below. 30 30 30 30 30 30 0 0 0 13 95 1 (b) (a) (w) (x) (y) (spx) (spy) (ca) (st) (pc) (sp) 1111 accumulator b register w register x register y register spx register spy register carry status program counter initial value: $0000, r/w not possible stack pointer initial value: $3ff, r/w not possible 0 0 initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: 1, r/w not possible figure 8 registers and flags accumulator (a) and b register (b): a and b are 4-bit registers, and are used to hold the results of alu (arithmetic and logical unit) operations and to transfer data between memory, i/o ports, and other registers.
hd404669 series 19 w register (w), x register (x), and y register (y): w is a 2-bit register and x and y are 4-bit registers. these registers are used in ram register indirect addressing. the y register is also used in d port addressing. spx register (spx) and spy register (spy): the spx and spy registers are 4-bit registers used to supplement the x and y registers. carry flag (ca): ca is a 1-bit flag that stores alu overflow generated by an arithmetic operation. ca is set to 1 when an overflow is generated, and is cleared to 0 after operations in which no overflow occurred. ca is also affected by the carry set/carry clear instructions (sec and rec), and by the rotate with carry instructions (rotl and rotr). during interrupt handling, ca is saved on the stack, and is restored from the stack by the rtni instruction. (but is not affected by the rtn instruction) status flag (st): st is a 1-bit flag that stores the results of arithmetic instructions, compare instructions, and bit test instructions, and is used as the branch condition for the br, brl, cal, and call conditional branch instructions. the contents of the st flag are held until the next arithmetic, compare, bit test, or conditional branch instruction is executed. after the execution of a conditional branch instruction, the value of st is set to 1 without regard to the condition. during interrupt handling, st is saved on the stack, and is restored from the stack by the rtni instruction. (but is not affected by the rtn instruction) program counter (pc): the pc is a 14-bit counter that indicates the rom address of the next instruction the cpu will execute. stack pointer (sp): the sp is a 10-bit register that indicates the ram address of the next stack frame in the stack area. the sp is initialized to $3ff by a reset. the sp is decremented by 4 by a subroutine call or by interrupt handling, and is incremented by 4 when the saved data has been restored by a return instruction. the upper 4 bits of the sp are fixed at 1111; the maximum number of stack levels is thus 16. in addition to the reset method described above, the sp can also be initialized to $3ff by clearing the reset stack pointer (rsp) in the interrupt control bits area with a ram bit manipulation instruction, i.e., rem or remd.
hd404669 series 20 reset the mcu can be reset by setting the reset pin high or by setting the stopc pin low*. when power is first applied, or when clearing subactive mode, watch mode, or stop mode, the reset input must be held for at least t rc to assure that the oscillation stabilization time (t rc ) condition is fulfilled. similarly, the stopc pin input must held for at least t rc when clearing stop mode with a stopc pin input to assure that the oscillator stabilizes. in all other cases, the mcu is reset by a reset input that is held for at least two instruction execution cycles. table 1 lists the section of the mcu that are initialized by a reset and the initial values. note: * the stopc pin reset is only effective in stop mode.
hd404669 series 21 table 1 initial values after mcu reset item abbr. initial value contents program counter (pc) $0000 indicates program execution point from start address of rom area status flag (st) 1 enables conditional branching stack pointer (sp) $3ff stack level 0 interrupt interrupt enable flag (ie) 0 inhibits all interrupts flags/mask interrupt request flag (if) 0 indicates there is no interrupt request interrupt mask (im) 1 prevents (masks) interrupt requests i/o port data register (pdr) all bits 1 enables output at level 1 data control register (dcd0) 0000 turns output buffer off (to high impedance) data control register (dcd1) --00 data control register (dcd2) 000- data control register (dcr0?cr4, dcr6?cr9) 0000 data control register (dcra) --00 port mode register a (pmra) --00 refer to description of port mode register a port mode register b (pmrb) 0000 refer to description of r port port mode register c bits 3, 1, 0 (pmrc3, pmrc1, pmrc0) 00- refer to description of port mode register c detection edge select registers 1 and 2 (esr1, 2) 0000 refer to description of interrupts timer/ counters, serial interface timer mode register a (tma) 0000 refer to description of timer mode register a section timer mode register c1 (tmc1) 0000 refer to description of timer mode register c1 timer mode register c2 (tmc2) -000 refer to description of timer mode register c2 timer mode register d1 (tmd1) 0000 refer to description of timer mode register d1 timer mode register d2 (tmd2) 0000 refer to description of timer mode register d2 serial mode register 1a (sm1a) 0000 refer to description of serial mode register 1a serial mode register 1b (sm1b) --x0 refer to description of serial mode register 1b prescaler s (pss) $000 refer to description of prescalers prescaler w (psw) $00 refer to description of prescalers timer counter a (tca) $00 refer to description of timer a timer counter c (tcc) $00 refer to description of timer c timer counter d (tcd) $00 refer to description of timer d
hd404669 series 22 item abbr. initial value contents timer/ counters, serial interface timer write register c (twcu, l) $x0 refer to description of timer write register c timer write register d (twdu, l) $x0 refer to description of timer write register d serial data register 1 (sr1u, l) $xx refer to description of serial data register 1 octal counter (oc1) 000 refer to description of serial interface dtmf tone generator mode register (tgm) 0000 refer to description of tone generator mode register tone generator control register (tgc) 000 - refer to description of tone generator control register comparator compare data register (cdr) --xx refer to description of compare data register compare enable register (cer) 0-00 refer to description of compare enable register bit registers low speed on flag (lson) 0 refer to description of operating modes watchdog timer on flag (wdon) 0 refer to description of timer c direct transfer on flag (dton) 0 refer to description of operating modes input capture status flag (icsf) 0 refer to description of timer d input capture error flag (icef) 0 refer to description of timer d others miscellaneous register (mis) 0000 refer to description of operating modes and pull-up and pull-down mos transistor control. system clock select register 1 bits 2 to 0 (ssr12 ?sr10) 000 refer to description of internal oscillator circuit and system clock select register 1 and 2 system clock select register 2 (ssr2) 0000 refer to description of internal oscillator circuit and system clock select register 1 and 2 bank register (v) - - -0 refer to description of ram memory map notes: 1. the statuses of other registers and flags after mcu reset are shown in the following table. 2. x indicates invalid value. ?indicates that the bit does not exist. item abbr. status after cancel-lation of stop mode by stopc input status after all other types of reset carry flag (ca) pre-stop-mode values are not guaranteed; values must be initialized by program pre-mcu-reset values are not guaranteed; values must be initialized by program accumulator (a) b register (b) w register (w) x/spx register (x/spx) y/spy register (y/spy) ram pre-stop-mode values are retained ram enable flag (rame) 1 0 port mode register c bit 2 (pmrc2) pre-stop-mode values are retained 0 system clock select register 1 bit 3 (ssr13)
hd404669 series 23 interrupts the mcu has 9 interrupt sources: five external signals ( int 0 , int 1 , int 2 ?nt 4 ), three timer/ counters (timers a, c, and d), serial interface (serial 1). an interrupt request flag (if), interrupt mask (im), and vector address are provided for each interrupt source, and an interrupt enable flag (ie) controls the entire interrupt process. as vector addresses are shared by interrupt sources timer c and int 3 , and timer d and int 4 , so the type of request that has occurred must be checked at the beginning of interrupt processing. interrupt control bits and interrupt processing: locations $000 to $003 and $022 to $023 in ram are reserved for the interrupt control bits which can be accessed by ram bit manipulation instructions. the interrupt request flag (if) cannot be set by software. mcu reset initializes the interrupt enable flag (ie) and the if to 0 and the interrupt mask (im) to 1. a block diagram of the interrupt control circuit is shown in figure 9, interrupt priorities and vector addresses are listed in table 2, and interrupt processing conditions for the 9 interrupt sources are listed in table 3. an interrupt request occurs when the if is set to 1 and the im is set to 0. if the ie is 1 at that point, the interrupt is processed. a priority programmable logic array (pla) generates the vector address assigned to that interrupt source. the interrupt processing sequence is shown in figure 10 and an interrupt processing flowchart is shown in figure 11. after an interrupt is acknowledged, the previous instruction is completed in the first cycle. the ie is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack during the second and third cycles, and the program jumps to the vector address to execute the instruction in the third cycle. program the jmpl instruction at each vector address, to branch the program to the start address of the interrupt program, and reset the if by a software instruction within the interrupt program. table 2 vector addresses and interrupt priorities reset/interrupt priority vector address reset, stopc * $0000 int 0 1 $0002 int 1 2 $0004 timer a 3 $0006 int 2 4 $0008 timer c, int 3 5 $000a timer d, int 4 6 $000c serial 1 7 $000e note: * the stopc interrupt request is valid only in stop mode.
hd404669 series 24 $000, 2 $000, 3 priority controller $001, 0 $001, 1 $001, 2 $001, 3 $002, 2 $002, 3 $003, 0 $003, 1 $003, 2 $003, 3 int 0 interrupt int 1 interrupt timer c interrupt timer d interrupt serial 1 interrupt timer a interrupt interrupt request if0 im0 if1 im1 ifta imta iftc imtc iftd imtd $000, 0 ie $022, 0 $022, 1 $022, 2 $022, 3 $023, 0 $023, 1 int 2 interrupt int 3 interrupt int 4 interrupt if2 im2 if3 im3 if4 im4 vector address ifs1 ims1 figure 9 interrupt control circuit
hd404669 series 25 table 3 interrupt processing and activation conditions interrupt source interrupt cuntrol bit int 0 int 1 timer a int 2 timer c or int 3 timer d or int 4 serial 1 ie 1 111 1 1 1 if0 . im0 1 000 0 0 0 if1 . im1 * 100 0 0 0 ifta . imta ** 10 0 0 0 if2 . im2 *** 1000 iftc . imtc + if3 . im3 * *** 10 0 iftd . imtd + if4 . im4 * *** * 10 ifs1 . ims 1 * *** * * 1 note: bits marked * can be either 0 or 1. their values have no effect on operation. instruction cycles 123456 instruction execution ie reset interrupt acceptance execution of jmpl instruction at vector address execution of instruction at start address of interrupt routine vector address generation note: * * stacking the stack is accessed and the ie reset after the instruction is executed, even if it is a 2-cycle instruction. figure 10 interrupt sequence
hd404669 series 26 power on no yes no yes no yes reset = "1"? interrupt request? mcu reset execute instruction ie = 1? accept interrupt yes int 0 interrupt? yes int 1 interrupt? yes timer a interrupt? yes int 2 interrupt? yes yes no no no no no no ie 0 stack (pc) stack (ca) stack (st) pc (pc)+1 pc $0002 pc $0004 pc $0006 pc $0008 pc $000a pc $000c pc $000e timer c or int 3 interrupt? timer d or int 4 interrupt? (serial 1 interrupt) figure 11 interrupt processing flowchart
hd404669 series 27 interrupt enable flag (ie: $000, bit 0): controls the entire interrupt process. it is reset by the interrupt processing and set by the rtni instruction, as listed in table 4. table 4 interrupt enable flag (ie: $000, bit 0) ie interrupt enabled/disabled 0 disabled 1 enabled external interrupt request flags (if0?f4: $000, $001, $022, $023): if0 and if1 are set at the falling edge of signals input to int 0 and int 1 , and if2?f4 are set at the rising or falling edge of signals input to int 2 ?nt 4 , as listed in table 5. the int 2 ?nt 4 interrupt edges are selected by the detection edge select registers (esr1, esr2: $026, $027) as shown in figures 12 and 13. bit initial value read/write bit name 3 0 w esr13 2 0 w esr12 0 0 w esr10 1 0 w esr11 detection edge selection register 1 (esr1: $026) esr11 0 1 esr10 0 1 0 1 int 2 detection edge no detection falling-edge detection rising-edge detection falling/rising-edge detection esr13 0 1 esr12 0 1 0 1 int 3 detection edge no detection falling-edge detection rising-edge detection falling/rising-edge detection figure 12 detection edge selection register 1 (esr1)
hd404669 series 28 bit initial value read/write bit name 3 0 w esr23 2 0 w esr22 0 0 w esr20 1 0 w esr21 detection edge selection register 2 (esr2: $027) esr21 0 1 esr20 0 1 0 1 int 4 detection edge no detection falling-edge detection rising-edge detection falling/rising-edge detection esr23 0 1 esr22 0 1 0 1 evnd detection edge no detection falling-edge detection rising-edge detection falling/rising-edge detection figure 13 detection edge selection register 2 (esr2) table 5 external interrupt request flags (if0?f4: $000, $001, $022, $023) if0?f4 interrupt request 0no 1 yes external interrupt masks (im0?m4: $000, $001, $022, $023): prevent (mask) interrupt requests caused by the corresponding external interrupt request flags, as listed in table 6. table 6 external interrupt masks (im0?m4: $000, $001, $022, $023) im0?m4 interrupt request 0 enabled 1 disabled (masked)
hd404669 series 29 timer a interrupt request flag (ifta: $001, bit 2): set by overflow output from timer a, as listed in table 7. table 7 timer a, c, d interrupt request flags (ifta: $001, bit 2, iftc: $002, bit 2, iftd: $003, bit 0) timer a, c, d interrupt request flags (ifta, iftc, iftd) interrupt request 0no 1 yes timer a interrupt mask (imta: $001, bit 3): prevents (masks) an interrupt request caused by the timer a interrupt request flag, as listed in table 8. table 8 timer a, c, d interrupt masks (imta: $001, bit 3, imtc: $002, bit 3, imtd: $003, bit 1) timer a, c, d interrupt masks (imta, imtc, imtd) interrupt?equest 0 enabled 1 disabled (masked) timer c interrupt request flag (iftc: $002, bit 2): set by overflow output from timer c, as listed in table 7. timer c interrupt mask (imtc: $002, bit 3): prevents (masks) an interrupt request caused by the timer c interrupt request flag, as listed in table 8. timer d interrupt request flag (iftd: $003, bit 0): set by overflow output from timer d, or by the rising or falling of signals input to evnd when the input capture function is used, as listed in table?. timer d interrupt mask (imtd: $003, bit 1): prevents (masks) an interrupt request caused by the timer d interrupt request flag, as listed in table 8. serial 1 interrupt request flag (ifs1: $003, bit 2): set when data transfer is completed or when data transfer is suspended, as listed in table 9. table 9 serial 1 interrupt request flag (ifs1: $003, bit 2) ifs1 interrupt request 0no 1 yes
hd404669 series 30 serial 1 interrupt mask (ims1: $003, bit 3): prevents (masks) an interrupt request caused by the serial 1 interrupt request flag, as listed in table 10. table 10 serial 1 interrupt mask (ims1: $003, bit 3) ims1 interrupt request 0 enabled 1 disabled (masked)
hd404669 series 31 operating modes the mcu has five operating modes as shown in table 11. the operations in each mode are listed in table 12. transitions between operating modes are shown in figure 14. table 11 operating modes and clock status mode name active standby stop watch subactive * 2 activation method reset cancellation, interrupt request, stopc cancellation in stop mode, stop/sby instruction in subactive mode (when direct transfer is selected) sby instruction stop instruction when tma3 = 0 stop instruction when tma3 = 1 stop/sby instruction in subactive mode (except when direct transition is specified) int 0 or timer a interrupt request from watch mode when lson = 1 status system oscillator operation operation stopped stopped stopped subsystem oscillator operation operation * 1 operation operation cancellation method reset input, stop/sby instruction reset input, interrupt request reset input, stopc input reset input, int 0 or timer a interrupt request reset input, stop/sby instruction notes: 1. operating or stopping the oscillator can be selected by setting bit 3 of the system clock select register (ssr: $029). 2. subactive mode is an optional function; specify it on the function option list.
hd404669 series 32 table 12 operations in low-power dissipation modes function stop mode watch mode standby mode subactive mode * 2 cpu reset retained retained operation ram retained retained retained operation timer a reset operation operation operation timer c reset stopped operation operation timer d reset stopped operation operation serial interface 1 reset stopped * 1 operation operation dtmf reset reset operation reset comparator reset stopped stopped operation i/o reset (high- impedance) retained retained operation notes: 1. when a clock is input in external clock mode, transmit/receive operations are performed, but interrupt operations are halted. 2. subactive mode is a function option, and should be specified in the function option list.
hd404669 series 33 reset by reset input or by watchdog timer f osc : f x : cpu : clk : per : oscillate oscillate stop f cyc f cyc f osc : f x : cpu : clk : per : oscillate oscillate stop f w f cyc f osc : f x : cpu : clk : per : oscillate oscillate f cyc f cyc f cyc f osc : f x : cpu : clk : per : oscillate oscillate f cyc f w f cyc f osc : f x : cpu : clk : per : stop oscillate f sub f w f sub f osc : f x : cpu : clk : per : stop stop stop stop stop f osc : f x : cpu : clk : per : stop oscillate stop f w stop f osc : f x : cpu : clk : per : stop oscillate stop f w stop standby mode stop mode (tma3 = 0, ssr13 = 1) watch mode subactive mode (tma3 = 1) (tma3 = 1, lson = 0) (tma3 = 1, lson = 1) sby interrupt sby interrupt stop int 0 , timer a stop 1. stop/sby (dton = 1, lson = 0) 2. stop/sby (dton = 0, lson = 0) 3. stop/sby (dton = don? care, lson = 1) f osc : f x : f cyc : f sub : f w : lson: dton: main oscillation frequency suboscillation frequency for time-base f osc /32 (selected by software) f osc /4, f osc /8, f osc /16 or f x /8 or f x /4 (software selectable) f x /8 system clock clock for time-base peripheral functions clock low speed on flag direct transfer on flag active mode notes: cpu : clk : per : f osc : f x : cpu : clk : per : stop oscillate stop stop stop (tma3 = 0, ssr13 = 0) reset1 reset2 rame = 0 rame = 1 int 0 , timer a (tma3 = 0) stop stopc stopc stop * 1 * 2 * 3 figure 14 mcu status transitions
hd404669 series 34 active mode: all mcu functions operate according to the clock generated by the system oscillator osc 1 and osc 2 . standby mode: in standby mode, the oscillators continue to operate, but the clocks related to instruction execution stop. therefore, the cpu operation stops, but all ram and register contents are retained, and the d or r port status, when set to output, is maintained. peripheral functions such as interrupts, timers, and serial interface continue to operate. the power dissipation in this mode is lower than in active mode because the cpu stops. (interrupts, timers, the serial interface, and other peripheral functions continue to operate. the exception is the comparator, which is halted.) the mcu enters standby mode when the sby instruction is executed in active mode. standby mode is terminated by a reset input or an interrupt request. if it is terminated by reset input, the mcu is reset as well. after an interrupt request, the mcu enters active mode and executes the next instruction after the sby instruction. if the interrupt enable flag is 1, the interrupt is then processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. figure 15 shows a flowchart of mcu operation. stop mode system clock oscillator started mcu reset system clock oscillator started stopc =0? rame=1 rame=0 interrupts enabled if0 im0 =1? if1 im1 =1? ifta imta =1? if2 im2 = 1? iftc imtc + if3 im3 =1? iftd imtd + if4 im4 =1? if =1, im=0, ie =1? no no yes yes yes yes yes yes yes yes yes no no no no no no no no yes * * * * no yes * only when clearing from standby mode. note: * standby mode watch mode reset=1? next instruction execution next instruction execution ifs1 ims1 =1 reset=1? figure 15 mcu operation flowchart
hd404669 series 35 stop mode: in stop mode, all mcu operations stop and ram data is retained. therefore, the power dissipation in this mode is the least of all modes. the osc 1 and osc 2 oscillator stops. for the x1 and x2 oscillator to operate or stop can be selected by setting bit 3 of the system clock select register 1 (ssr1: $029; operating: ssr13 = 0, stop: ssr3 = 1) (figure 24). the mcu enters stop mode if the stop instruction is executed in active mode when bit 3 of timer mode register a (tma: $008) is set to 0 (tma3 = 0) (figure 40). stop mode is cleared by a reset or stopc * input. the reset or stopc input must be held for at least the oscillation stabilization time (t rc ) as shown in figure 16. (refer to the "ac characteristics" section.) in either of these cases, the mcu will start program execution from the program start address (location 0). however, the value of the ram enable flag (rame: $021,3) will be different in these cases. in particular, rame will be set to 0 for a reset input and will be set to 1 for a stopc input. also note that while a reset input is effective in all mcu modes, stopc is only effective in stop mode, and is ignored in all other modes. if a program needs to determine if stop mode was cleared by a stopc input (for example, if the program intends to use the contents of ram that were stored before stop mode was entered after returning to active mode) the program should test the ram enable flag with a test instruction at the start of the program. note: * if stop mode is to be cleared by a s t op c input, applications should set bit 2 of port mode register c (pmrc) to 1 (pmrc2 = 1) before switching to stop mode. stop mode oscillator internal clock stop instruction execution (at least equal to oscillation stabilization time t rc ) t res reset stopc figure 16 timing of stop mode cancellation watch mode: in watch mode, the clock function (timer a) using the x1 and x2 oscillator, but other function operations stop. therefore, the power dissipation in this mode is the second least to stop mode, and this mode is convenient when only clock display is used. in this mode, the osc 1 and osc 2 oscillator stops, but the x1 and x2 oscillator operates. the mcu is switched to watch mode by executing a stop instruction while tma3 = 1 in active mode, or by executing a stop/sby instruction while lson is set to 1 or dton is cleared to 0 in subactive mode. watch mode is terminated by a reset input or a timer-a/ int 0 interrupt request. for details of reset input, refer to the stop mode section. when terminated by a timer-a/ int 0 interrupt request, the mcu enters active mode if lson = 0, or subactive mode if lson = 1. after an interrupt request is generated, the time required to enter active mode is t rc for a timer a interrupt, and t x ?where t + t rc < t x < 2t + t rc ) for an int 0 interrupt, as shown in figures 17 and 18.
hd404669 series 36 operation during mode transition is the same as that at standby mode cancellation (figure 15). t rc t t x t t: t : interrupt frame period oscillation stabilization time rc (during the transition from watch mode to active mode only) interrupt strobe int 0 interrupt request generation active mode watch mode active mode oscillation stabilization time note: if the time from the fall of the int 0 signal until the interrrupt is accepted and active mode is entered is designated tx, then tx will be in the following range: t + t rc < t x < 2t + t rc figure 17 interrupt frame
hd404669 series 37 subactive mode: the osc 1 and osc 2 oscillator stops and the mcu operates with a clock generated by the x1 and x2 oscillator. in this mode, functions other than the dtmf generation circuit operate, but since the operating clocks are slow, power consumption is the lowest after watch mode. the cpu instruction execution speed can be selected as 244 m s or 122 m s by setting bit 2 (ssr12) of the system clock select register (ssr1: $029). note that the ssr12 value must be changed in active mode. if the value is changed in subactive mode, the mcu may malfunction. when the stop or sby instruction is executed in subactive mode, the mcu enters either watch or active mode, depending on the statuses of the low speed on flag (lson: $020, bit 0) and the direct transfer on flag (dton: $020, bit 3). subactive mode is an optional function that the user must specify on the function option list. interrupt frame: in watch and subactive modes, f clk is applied to timer a and the int 0 i circuit. prescaler w and timer a operate as the time-base and generate the timing clock for the interrupt frame. three interrupt frame periods (t) can be selected by setting the miscellaneous register (mis: $00c) (figure 18). in watch and subactive modes, the timer-a/ int 0 interrupt is generated synchronously with the interrupt frame. the interrupt request is generated synchronously with the interrupt strobe timing except during transition to active mode. an overflow and interrupt request in timer a is generated synchronously with the interrupt strobe timing. bit initial value read/write bit name 3 0 w mis3 2 0 w mis2 0 0 w mis0 1 0 w mis1 miscellaneous register (mis: $00c) mis1 0 mis0 t * 0 0.24414 ms t rc 0.12207 ms 0.24414 ms 7.8125 ms 31.25 ms oscillation circuit conditions external clock input ceramic oscillator crystal oscillator 0 1 1 1 0 1 15.625 ms 62.5 ms not used not used notes: 1. 2. values of t and t rc when a 32.768-khz crystal oscillator is used to pins x1 and x2. the value is applied only when direct transfer operation is used. buffer control. see figure 37 in the pull-up and pull-down mos transistor control section mis3 mis2 1 * 1 * 2 figure 18 miscellaneous register (mis)
hd404669 series 38 direct transition from subactive mode to active mode: available by controlling the direct transfer on flag (dton: $020, bit 3) and the low speed on flag (lson: $020, bit 0). the procedures are described below: set lson to 0 and dton to 1 in subactive mode. execute the stop or sby instruction. the mcu automatically enters active mode from subactive mode after waiting for the mcu internal processing time and oscillation stabilization time (figure 19). notes: 1. the dton flag can be set only in subactive mode. it is always reset in active mode. 2. the transition time (t d ) from subactive mode to active mode: t rc < t d < t + t rc subactive mode interrupt strobe direct transfer completion timing mcu internal processing time oscillation stabilization time active mode t t t rc t: t : t : rc d d stop/sby instruction execution (set lson = 0, dton = 1) interrupt frame period oscillation stabilization time direct transition time figure 19 direct transition timing mcu operation sequence: the mcu operates in the sequence shown in figure 20. it is reset by an asynchronous reset input, regardless of its status. with the ie flag cleared and an interrupt request flag set together with its interrupt mask cleared, if a stop/sby instruction is executed, the instruction is cancelled (regarded as an nop) and the following instruction is executed. before executing a stop/sby instruction, make sure all interrupt request flags are cleared or all interrupts are masked.
hd404669 series 39 stop/sby instruction if = 1 and im = 0? hardware nop execution ? pc (pc)+1 ? pc (pc)+1 mcu operation cycle standby/watch mode if = 1 and im = 0? hardware nop execution instruction execution stop mode no yes ie = 0 yes no yes note: * refer to figure 15, flowchart for exiting low power modes, for if and im operation. stopc = 0? rame = 1 reset mcu no no yes * interrupt service routine figure 20 mcu operating (low-power mode operation) notes: when the mcu is in watch mode or subactive mode, if the high level period before the falling edge of i nt 0 is shorter than the interrupt frame, i nt 0 is not detected. also, if the low level period after the falling edge of i nt 0 is shorter than the interrupt frame, i nt 0 is not detected. edge detection is shown in figure 21. the level of the int 0 signal is sampled by a sampling clock. when this sampled value changes to low from high, a falling edge is detected.
hd404669 series 40 in figure 22(a), the level of the i nt 0 signal is sampled by an interrupt frame. in (a) the sampled value is low at point a, and also low at point b. therefore, a falling edge is not detected. in (b), the sampled value is high at point a, and also high at point b. a falling edge is not detected in this case either. when the mcu is in watch mode or subactive mode, keep the high level and low level period of int 0 longer than interrupt frame. high low int sampling 0 low figure 21 edge detection a: low b: low int interrupt frame 0 a: high b: high int interrupt frame 0 (a) high level period (b) low level period figure 22 sampling example
hd404669 series 41 internal oscillator circuit a block diagram of the clock generation circuit is shown in figure 23. as shown in table 13, a ceramic oscillator or crystal oscillator can be connected to osc 1 and osc 2 , and a 32.768-khz oscillator can be connected to x1 and x2. the system oscillator can also be operated by an external clock. set bits 0 and 1 (ssr10, ssr11) of system clock select register 1 (ssr1: $029) and bits 2 and 3 (ssr22, ssr23) of system clock select register 2 (ssr2: $02a) according to the frequency of the oscillator connected to osc 1 and osc 2 (figures 24 and 25). the system clock division ratio can be set with bits 0 and 1 (ssr20, ssr21) of system clock select register 2 (ssr2: $02a). the value set in these bits does not become valid until watch mode is entered. therefore, the system clock must be halted temporarily when changing the division ratio. the system clock division ratio immediately after a reset or when stop mode is cleared can be selected by means of the sel pin level, division-by-4 being selected when the sel pin is at vcc potential, and division-by-32 when at gnd potential. note: if the system clock select register 1 and 2 (ssr1, ssr2: $029, $02a) setting does not match the oscillator frequency, dtmf generation circuit and subsystems using the 32.768-khz oscillation will malfunction. osc 2 osc 1 x1 x2 system clock oscillator sub- system clock oscillator 1/4, 1/8, 1/16 or 1/32 division circuit timing generation circuit system clock selection circuit cpu with rom, ram, registers, flags, and i/o internal peripheral module interrupts time base interrupt time-base clock selection circuit 1/8 or 1/4 division circuit timing generation circuit timing generation circuit 1/8 division circuit f w f sub t subcyc lson tma3 bit f cyc t cyc f osc f x t wcyc cpu per clk figure 23 clock generation circuit
hd404669 series 42 bit initial value read/write bit name 3 0 w ssr13 2 0 w ssr12 0 0 w ssr10 1 0 w ssr11 system clock select register 1 (ssr1: $029) ssr12 0 1 ratio selection f sub = f x /8 f sub = f x /4 ssr13 0 1 32-khz oscillation stop oscillation operates in stop mode oscillation stops in stop mode 32-khz oscillation division ssr23 0 1 system clock selection 400 khz 800 khz 2 mhz 4 mhz 3.58 mhz 8 mhz 7.16 mhz ssr22 0 1 0 1 ssr11 0 1 1 ssr10 0 1 0 1 1 note: ssr13 is cleared only by a reset input. ssr13 will not be cleared by a stopc input during stop mode, and will retain its value. ssr13 will also not be cleared upon entering stop mode. figure 24 system clock select register 1 (ssr1) ssr21 ssr20 0 1 0 1 0 1 system clock division ratio selection * 1 division by 4 division by 8 division by 16 division by 32 system clock select register 2 (ssr2: $02a) 0 1 0 1 0 1 ssr23 ssr22 system clock selection * 2 selected from 400 khz, 800 khz, 2 mhz, 4 mhz 3.58mhz 8mhz 7.16mhz notes : * 1 * 2 the dtmf generation circuit frequencies are not affected by the system clock division ratio setting. see system clock select register 1 (ssr1). bit initial value read/write bit name 3 0 w ssr23 2 0 w ssr22 0 0 w ssr20 1 0 w ssr21 figure 25 system clock select register 2 (ssr2)
hd404669 series 43 table 13 oscillator circuit examples circuit configuration circuit constants external clock operation external oscillator osc open 1 osc 2 ceramic oscillator (osc 1 , osc 2 ) osc 2 c 1 2 c osc 1 r f ceramic oscillator gnd ceramic oscillator: csb400p22 (murata) csb400p (murata) r f = 1 m w 20% c 1 = c 2 = 220 pf 5% ceramic oscillator: csb800j122 (murata), csb800j (murata) r f = 1 m w 20% c 1 = c 2 = 220 pf 5% ceramic oscillator: csa2.00mg (murata) r f = 1 m w 20% c 1 = c 2 = 30 pf 20% ceramic oscillator: csa4.00mg (murata) r f = 1 m w 20% c 1 = c 2 = 30 pf 20% ceramic oscillator: csa3.58mg (murata) r f = 1 m w 20% c 1 = c 2 = 30 pf 20% ceramic oscillator: csa8.00mt (murata) r f = 1 m w 20% c 1 = c 2 = 30 pf 20% crystal oscillator (osc 1 , osc 2 ) osc 1 c 1 2 c osc 2 crystal oscillator gnd l s c r s r f c 0 osc 1 osc 2 r f = 1 m w 20% c 1 = c 2 = 10 to 22pf 20% crystal oscillator: equivalent circuit at left c 0 =7pf max r s = 100 w max f = 400khz, 800khz, 2mhz, 3.58mhz, 4mhz, 7.16mhz, 8mhz
hd404669 series 44 circuit configuration circuit constants crystal oscillator (x1, x2) x1 c 1 2 c x2 crystal oscillator gnd l s c r s c 0 x1 x2 crystal oscillator: 32.768 khz: mx38t (nippon denpa) c 1 = c 2 = 20 pf 20% r s =14 k w c 0 =1.5 pf notes: 1. circuit constants differ by the different types of crystal oscillators, ceramic oscillators, and with the stray capacitance of the board, so consult the manufacturer of the oscillator to determine the circuit parameters. 2. the wiring between the osc 1 , osc 2 (x1 and x2 pins), and the other elements should be as short as possible, and must not cross other wiring. refer to figure 26. 3. if not using a 32.768-khz crystal oscillator, fix the x1 pin to v cc and leave the x2 pin open. gnd gnd x2 x1 reset osc 2 osc 1 test figure 26 typical layouts of crystal and ceramic oscillator
hd404669 series 45 input/output the mcu has 47 input/output pins (d 0 to d 5 , d 9 to d 11 , r0 0 to r4 3 and r6 0 to ra 1 ) and 5 input pins (d 12 , d 13 , rd 0 , rd 1 and re 0 ). the features are described below. four pins d 0 to d 3 are high source current (10 ma maximum) input/output pins. five pins d 4 , d 5 , and d 9 to d 11 are high sink current (15 ma maximum) input/output pins. certain of these input and output pins have shared functions with timers, the serial interface, and other peripheral functions. the d 12 , d 13 , r0, r3 0 , r3 2 , r4, rd 0 , rd 1 and re 0 pins are shared function pins. the use of these pins as peripheral function pins takes precedence over their use as the d and r port pins. pins that are set to function as peripheral function pins are switched automatically between their various functions and between the input and output directions according to their specifications under the peripheral function setting. input or output selection for input/output pins and port or peripheral function selection for multiplexed pins are set by software. peripheral function output pins are all cmos outputs. however, the so 1 pin and the r4 3 port pin can be set to function as nmos open drain outputs by software. since the mcu goes to the reset state internally after a reset and in stop mode, the peripheral function settings for these pins are cleared. furthermore, since the data control registers (dcd and dcr) are also reset, the input/output pins go to the high-impedance state. the d 0 to d 3 pin circuits include pull-down mos transistors, and all the other pin circuits include pull- up mos transistors. note that the on/off states of the pull-up and pull-down mos transistors can be set independently of the setting for use as peripheral function pins. i/o buffer configurations are shown in figures 27 and 28, and i/o pin circuit structures are listed in tables 14 and 15. v cc v cc pull-up control signal buffer control signal output data input data hlt mis3 dcd,dcr pdr input control signal pull-up mos figure 27 i/o buffer configuration (with pull-up mos)
hd404669 series 46 v cc buffer control signal output data input data dcd pdr input control signal pull-down mos pull-down mos control signal hlt mis3 figure 28 i/o buffer configuration (with pull-down mos) table 14 i/o pin control by register settings (with pull-up mos) mis3 (bit 3 of mis) 0 1 dcd, dcr 0 1 0 1 pdr 010 10 101 cmos buffer pmos on on nmos on on pull-up mos on on note: 1. ?indicates off status. 2. pdr is not assigned to a ram address. it is accessed with special input/output instructions. table 15 i/o pin control by register settings (with pull-down mos) mis3 (bit 3 of mis) 0 1 dcd 0 1 0 1 pdr 010 10 101 cmos buffer pmos on on nmos on on pull-down mos onon note: 1. ?indicates off status. 2. pdr is not assigned to a ram address. it is accessed with special input/output instructions.
hd404669 series 47 table 16 input/output pin circuit configurations i/o pin type circuit configuration relevant pins input/output pins v cc v cc pull-up control signal buffer control signal output data input data hlt mis3 dcd,dcr pdr input control signal d 4 , d 5 , d 9 ?d 11 r0 0 ?0 3 r1 0 ?1 3 r2 0 ?2 3 r3 0 ?3 3 r4 0 ?4 2 r6 0 ?6 3 r7 0 ?7 3 r8 0 ?8 3 r9 0 ?9 3 ra 0 , ra 1 v cc buffer control signal output data input data dcd pdr input control signal pull-down control signal hlt mis3 d 0 ? 3 pull-up control signal buffer control signal output data input data hlt mis3 dcr pdr input control signal mis2 v cc v cc r4 3 input pins input data input control signal d 12 , d 13 rd 0, rd 1, re 0
hd404669 series 48 table 16 input/output pin circuit configurations (cont) i/o pin type circuit configuration relevant pins peripheral function input/output pins v cc v cc pull-up control signal output data input data hlt mis3 sck 1 sck 1 sck 1 output pins pull-up control signal pmos control signal output data hlt mis3 so 1 mis2 v cc v cc so 1 pull-up control signal output data hlt mis3 toc,tod v cc v cc toc, tod input pins input data hlt mis3 pdr si 1 , int 1 ,etc. v cc si 1 , int 1 , int 2 , int 3 , int 4 , evnd input data int 0 , stopc , reset int 0 , stopc reset note: in a reset and in stop mode, since the i/o control registers are reset, input/output pins go to the high- impedance state and peripheral function selections are cleared.
hd404669 series 49 d port the d port consists of 9 input/output pins and 2 input-only pins that can be addressed individually on a per- bit basis. the d 0 to d 3 pins are high source current input/output pins and the d 4 , d 5 , and d 9 to d 11 pins are high sink current input/output pins. the d 12 and d 13 pins are input-only pins. the d 0 to d 5 and d 9 to d 11 pins can be set or reset by the sed/red and sedd/redd instructions. the output data is stored in the port data register for the pin. all the d port pins can be tested using the td and tdd instructions. the d port data control registers (dcd0 to dcd2: $02c to $02e) are used to turn the d 0 to d 5 and d 9 to d 11 pin output buffers on and off. the dcd registers are mapped to addresses in the ram area. (figure 29.) the d 12 and d 13 pins have shared functions as internal peripheral function pins and the stopc and int 0 pins. port mode register c (pmrc: $025) bits 2 and 3 (pmrc2 and pmrc3) are used to switch the functions of these pins. (figure 32.)
hd404669 series 50 bit initial value read/write bit name 3 0 w dcd03, 2 0 w dcd02, 0 0 w dcd00 1 0 w dcd01 dcd0 to dcd2 data control register (dcd0 to 2: $02c to $02e) (dcr0 to 4, dcr6 to a: $030 to $034, $036 to $03a) dcd23 dcd22 dcd10 dcd21 bit initial value read/write bit name note: other bits are not used. 3 0 w dcr03 2 0 w dcr02 0 0 w dcr00 1 0 w dcr01 dcr0 to dcr4 dcr6 to dcra dcr43 dcr42 dcr40 dcr41 dcr61 dcr60 dcr62 dcr63 dcra1 dcra0 dcr92 dcr93 all bits cmos buffer control 0 cmos buffer off (high-impedance) 1 cmos buffer active correspondence between ports and dcd/dcr bits register name bit 3 bit 2 bit 1 bit 0 dcd0 d 3 d 2 d 1 d 0 dcd1 d 5 d 4 dcd2 d 11 d 10 d 9 dcr0 r0 3 r0 2 r0 1 r0 0 dcr1 r1 3 r1 2 r1 1 r1 0 dcr2 r2 3 r2 2 r2 1 r2 0 dcr3 r3 3 r3 2 r3 1 r3 0 dcr4 r4 3 r4 2 r4 1 r4 0 dcr6 r6 3 r6 2 r6 1 r6 0 dcr7 r7 3 r7 2 r7 1 r7 0 dcr8 r8 3 r8 2 r8 1 r8 0 dcr9 r9 3 r9 2 r9 1 r9 0 dcra ra 1 ra 0 figure 29 data control registers (dcd, dcr)
hd404669 series 51 r port the r port consist of 38 input/output pins and 3 input pins that can be addressed in groups of 4 bits. data can be input using the lar and lbr instructions, and data can be output using the lra and lrb instructions. output data is stored in the port data register for the corresponding pin. the r port data control registers (dcr0 to dcr4 and dcr6 to dcra: $030 to $034, and $036 to $03a) are used to turn the r port output buffers on and off. the dcr registers are mapped to addresses in the ram area. (figure 29.) the r0 0 to r0 4 port pins have shared functions as the external interrupt input pins int 1 to int 4 . port mode register b (pmrb $024) is used to set these pins to their peripheral function usage. (figure 31.) the r4 0 port pin has a shared function as the evnd peripheral function pin. port mode register c (pmrc: $025) bit 1 (pmrc1) is used to switch the function of this pin. (figure 32.) the r3 1 and r3 2 port pins have shared functions as the toc and tod peripheral function pins. timer mode register c2 (tmc2: $014) bits 0 to 2 (tmc20 to tmc22) and timer mode register d2 (tmd2: $015) are used to set these pins to their peripheral function usage. (figures 33 and 34.) the r4 1 to r4 3 port pins have shared functions as the sck 1 , si 1 , and so 1 peripheral function pins. serial mode register 1a (sm1a: $005) bit 3 (sm1a3) and port mode register a (pmra: $004) bits 0 and 1 (pmra0 and pmra1) are used to set these pins to their peripheral function usage. (figures 30 and 35.) the r4 3 /so 1 pin can be set to function as an nmos open drain output with the output buffer off. miscellaneous register (mis: $00c) bit 2 (mis2) is used for this setting. (figure 37.) the rd 0 and rd 1 port pins have shared functions as the comp 0 and comp 1 peripheral function pins. the compare enable register (cer: $018) is used to set these pins to their comparator pin functions. (figure 36.) bit initial value read/write bit name 3 not used 2 not used 0 0 w pmra0 1 0 w pmra1 pmra0 0 1 r4 3 /so 1 mode selection r4 3 so 1 port mode register a (pmra: $004) pmra1 0 1 r4 2 /si 1 mode selection r4 2 si 1 figure 30 port mode register a (pmra)
hd404669 series 52 bit initial value read/write bit name 3 0 w pmrb3 2 0 w pmrb2 0 0 w pmrb0 1 0 w pmrb1 pmrb0 0 1 r0 0 / int 1 mode selection r0 0 int 1 port mode register b (pmrb: $024) pmrb1 0 1 r0 1 /int 2 mode selection r0 1 int 2 pmrb2 0 1 r0 2 /int 3 mode selection r0 2 int 3 pmrb3 0 1 r0 3 /int 4 mode selection r0 3 int 4 figure 31 port mode register b (pmrb) bit initial value read/write bit name 3 0 w pmrc3 2 0 w pmrc2 0 not used 1 0 w pmrc1 port mode register c (pmrc: $025) pmrc1 0 1 r4 0 /evnd mode selection r4 0 evnd pmrc2 0 1 d 12 stopc pmrc3 0 1 d 13 d 13 / int 0 mode selection int 0 d 12 / stopc mode selection figure 32 port mode register c (pmrc)
hd404669 series 53 bit initial value read/write bit name 3 not used 2 0 r/w tmc22 0 0 r/w tmc20 1 0 r/w tmc21 timer mode register c2 (tmc2: $014) tmc22 tmc20 0 1 0 1 0 1 0 1 tmc21 0 1 0 1 0 1 r3 1 /toc mode selection r3 1 toc toc toc toc r3 1 port toggle output 0 output 1 output not used pwm output figure 33 timer mode register c2 (tmc2) bit initial value read/write bit name 3 0 r/w tmd23 2 0 r/w tmd22 0 0 r/w tmd20 1 0 r/w tmd21 timer mode register d2 (tmd2: $015) tmd22 tmd20 0 1 0 1 0 1 0 1 tmd21 0 1 0 1 0 1 r3 2 /tod mode selection r3 2 tod tod tod tod r3 2 r3 2 port toggle output 0 output 1 output not used pwm output input capture (r3 2 port) tmd23 0 1 : don? care figure 34 timer mode register d2 (tmd2)
hd404669 series 54 bit initial value read/write bit name 3 0 w sm1a3 2 0 w sm1a2 0 0 w sm1a0 1 0 w sm1a1 serial mode register 1a (sm1a: $005) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 output output output output output output output input prescaler prescaler prescaler prescaler prescaler prescaler system clock external clock ? 2048 ? 512 ? 128 ? 32 ? 8 ? 2 prescaler division ratio sm1a2 sm1a0 sm1a1 clock source sm1a3 0 1 r4 1 / sck 1 mode selection sck 1 r4 1 sck 1 figure 35 serial mode register 1a (sm1a) 0 1 : don't care 0 1 comp 0 comp 1 not used analog input pin selection comparator operation selection compare enable register (cer: $018) 0 1 normal operation (digital input mode): rd 0 /comp 0 and rd 1 /comp 1 pins function as r port pins comparator operation (analog input mode): rd 0 /comp 0 and rd 1 /comp 1 pins function as comparator pins bit initial value read/write bit name 3 0 w cer3 2 not used 0 0 w cer0 1 0 w cer1 cer3 cer1 cer0 figure 36 compare enable register (cer)
hd404669 series 55 pull-up and pull-down mos transistor control the d 4 , d 5 , d 9 to d 11 , and the r port pins have built-in pull-up mos transistors that can be controlled by software, and the d 0 to d 3 pins have built-in pull-down mos transistors that can be controlled by software. the on/off status of all these transistors is controlled by bit 3 (mis3) of the miscellaneous register (mis: $00c), and the on/off status of an individual transistor can also be controlled by the port data register (pdr) of the corresponding pin?nabling on/off control of that pin alone (tables 14, 15 and figure 37). the on/off status of each transistor and the peripheral function mode of each pin can be set independently. bit initial value read/write bit name 3 0 w mis3 2 0 w mis2 0 0 w mis0 1 0 w mis1 mis2 cmos buffer on/off selection for pin r4 3 /so 1 miscellaneous register (mis: $00c) 0 1 active off refer to figure 18 in the operation modes section. t rc selection. mis3 0 1 pull-up/pull-down mos transistor control off active mis1 mis0 figure 37 miscellaneous register (mis) how to deal with unused i/o pins: i/o pins that are not needed by the user system (floating) must be connected to v cc to prevent lsi malfunctions due to noise. these pins must either be pulled up to v cc by their pull-up mos transistors or by resistors of about 100 k w . pins provided with pull-down mos should be pulled down to gnd potential with the built-in pull-down mos or connected to gnd.
hd404669 series 56 prescalers the mcu has the following two prescalers, s and w. the prescalers operating conditions are listed in table 17, and the prescalers output supply is shown in figure 38. the timers a, c, d input clocks except external events, the serial transmit clock except the external clock, are selected from the prescaler outputs, depending on corresponding mode registers. table 17 prescaler operating conditions prescaler input clock reset conditions stop conditions prescaler s system clock (in active and standby mode), subsystem clock (in subactive mode) mcu reset mcu reset, stop mode, watch mode prescaler w clock derived by dividing subsystem clock 32.768 khz oscillation by 8 mcu reset, software * mcu reset, stop mode note: * if bits tma3 to tma1 in timer mode register a (tma) are all set to 1, psw is cleared to $00. timer a timer c timer d serial interface 1 subsystem clock prescaler w system clock clock selector prescaler s figure 38 prescaler output supply prescaler operation prescaler s: 11-bit counter that inputs the system clock signal. after being reset to $000 by mcu reset, prescaler s divides the system clock. prescaler s keeps counting, except in watch and stop modes and at mcu reset. prescaler w: five-bit counter that inputs the x1 input clock signal (32-khz crystal oscillation) divided by eight. after being reset to $00 by mcu reset, prescaler w divides the input clock. prescaler w can be reset by software.
hd404669 series 57 timers the mcu has three timer/counters (a, c, d). timer a: free-running timer timer c: multifunction timer timer d: multifunction timer timer a is an 8-bit free-running timer. timers c, d are 8-bit multifunction timers, whose functions are listed in table 18. the operating modes are selected by software. table 18 timer functions functions timer a timer c timer d clock prescaler s available available available source prescaler w available external event available timer free-running available available available functions time-base available event counter available reload available available watchdog available input capture available timer toggle available available outputs 0 output available available 1 output available available pwm available available note: ?implies not available. timer a timer a functions: timer a has the following functions. free-running timer clock time-base the block diagram of timer a is shown in figure 39.
hd404669 series 58 1/4 1/2 32.768-khz oscillator system clock prescaler w (psw) selector selector prescaler s (pss) selector internal data bus timer a interrupt request flag (ifta) clock overflow timer counter a (tca) timer mode register a (tma) 3 2 f 1/2 tw cyc f tw cyc per 2 4 8 32 128 512 1024 2048 ? ? ? ? ? ? ? ? 2 8 16 32 ? ? ? ? w w data bus clock line signal line figure 39 block diagram of timer a timer a operations free-running timer operation: the timer a input clock is selected by timer mode register a (tma: $008). timer a is reset to $00 by an mcu reset, and counts up each time the input clock is input. when the input clock is input after the timer a value reaches $ff, overflow output is generated, and the timer a value becomes $00. the generated overflow output sets the timer a interrupt request flag (ifta: $001, 2). timer a continues counting up after the count value returns to $00, so that an interrupt is generated regularly every 256 input clock cycles. realtime clock time base operation: timer a can be used as the realtime clock time base by setting bit 3 (tma3) of timer mode register a to 1. as the prescaler w output is input to timer counter a (tca), interrupts are generated with accurate timing using the 32.768 khz crystal oscillator as the basic clock.when timer a is used as the realtime clock time base, prescaler w and timer counter a (tca) can be reset to $00 by the program. registers for timer a operation timer a operating modes are set by the following registers. timer mode register a (tma: $008): four-bit write-only register that selects timer a? operating mode and input clock source as shown in figure 40.
hd404669 series 59 bit initial value read/write bit name 3 0 w tma3 2 0 w tma2 0 0 w tma0 1 0 w tma1 timer mode register a (tma: $008) 0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 pss pss pss pss pss pss pss pss psw psw psw psw operating mode timer a mode tma3 tma1 tma2 tma0 source prescaler 2048t cyc 1024t cyc 512t cyc 128t cyc 32t cyc 8t cyc 4t cyc 2t cyc input clock frequency 0 1 1 32t wcyc 16t wcyc 8t wcyc 2t wcyc 1/2t wcyc time-base mode 0 0 1 1 0 1 1 : don? care note: 1. 2. 3. t wcyc = 244.14 m s (when a 32.768-khz crystal oscillator is used) timer counter overflow output period (seconds) = input clock period (seconds) 256. the division ratio must not be modified during time-base mode operation, otherwise an overflow cycle error will occur. not used reset psw and tca figure 40 timer mode register a (tma)
hd404669 series 60 timer c timer c functions: timer c has the following functions. free-running/reload timer watchdog timer timer output operation (toggle, 0, 1, and pwm outputs) the block diagram of timer c is shown in figure 41.
hd404669 series 61 timer output control logic system clock timer output control timer c interrupt request flag (iftc) timer write register c (twcl) (twcu) 2 4 8 32 128 512 1024 ? per 3 3 4 4 4 clock overflow toc watchdog on flag (wdon) watchdog timer control logic system reset signal 2048 timer read register cl (trcl) timer counter c (tccl) (tccu) timer mode register c1 (tmc1) data bus clock line signal line timer mode register c2 (tmc2) timer read register cu (trcu) prescaler s (pss) selector free-running/reload control internal data bus figure 41 block diagram of timer c
hd404669 series 62 timer c operations free-running/reload timer operation: the free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register c1 (tmc1: $00d). timer c is initialized to the value set in timer write register c (twcl: $00e, twcu: $00f) by software and incremented by one at each clock input. if an input clock is applied to timer c after it has reached $ff, an overflow is generated. in this case, if the reload timer function is enabled, timer c is initialized to its initial value set in timer write register c (twcl: $00e, twcu: $00f); if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. the overflow sets the timer c interrupt request flag (iftc: $002, bit 2 ). the timer c interrupt request flag is reset by the program, an mcu reset or a transition to stop mode. for details, see figure 3, configuration of interrupt control bits and register flag area, and table 1, initial values after mcu reset. watchdog timer operation: timer c is used as a watchdog timer for detecting out-of-control program routines by setting the watchdog on flag (wdon: $020, bit 1) to 1. if a program routine runs out of control and an overflow is generated, the mcu is reset. program run can be controlled by initializing timer c by software before it reaches $ff. timer output operation: the following four output modes can be selected for timer c by setting timer mode register c2 (tmc2: $014). with timer c, the r3 1 /toc pin is designated as the toc pin, and toggle waveform output, low-level output, high-level output, or pwm waveform output can be selected, by timer mode register c2 (tmc2: $014). toc pin output is initialized to the low level by an mcu reset. toggle output with toggle output, the output level is changed upon input of the next clock pulse after the timer c value reaches $ff. use of this function in combination with the reload timer allows a clock signal with any period to be output, enabling it to be used as buzzer output. the output waveform is shown in figure 42. low-level output with low-level output, the output is changed to the low level when timer c overflows. this function should be used when the output is high. high-level output with high-level output, the output is changed to the high level when timer c overflows. this function should be used when the output is low. pwm output with pwm output, variable-duty pulses are output. the output waveform is as shown in figure 42, according to the contents of timer mode register c1 (tmc1: $00d) and timer write register c (twcl: $00e, twcu: $00f).
hd404669 series 63 t (n + 1) t 256 t t (256 ?n) tmc13 = 0 tmc13 = 1 tmd13 = 0 (free-running timer) tmd13 = 1 (reload timer) 256 clock cycles 256 clock cycles free-running timer toggle output waveform (timers c and d) pwm output waveform (timers c and d) (256 ?n) clock cycles (256 ?n) clock cycles reload timer notes: t: n: counter input clock period the clock input source and division ratio are controlled by timer mode register c1 and timer mode register d1. value in timer write register c or timer write register d (when n = 255 (= $ff), pwm output is always fixed low.) figure 42 timer output waveforms
hd404669 series 64 registers for timer c operation by using the following registers, timer c operation modes are selected and the timer c count is read and written. timer mode register c1 (tmc1: $00d) timer mode register c2 (tmc2: $014) timer write register c (twcl: $00e, twcu: $00f) timer read register c (trcl: $00e, trcu: $00f) timer mode register c1 (tmc1: $00d): four-bit write-only register that selects the free-running/reload timer function, and the prescaler division ratio as shown in figure 43. it is reset to $0 by mcu reset or in stop mode. writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register c1 write instruction. setting timer c? initialization by writing to timer write register c (twcl: $00e, twcu: $00f) must be done after a mode change becomes valid. bit initial value read/write bit name 3 0 w tmc13 2 0 w tmc12 0 0 w tmc10 1 0 w tmc11 timer mode register c1 (tmc1: $00d) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2048t cyc 1024t cyc 512t cyc 128t cyc 32t cyc 8t cyc 4t cyc 2t cyc tmc12 tmc10 tmc11 tmc13 0 1 free-running/reload timer selection free-running timer reload timer input clock period figure 43 timer mode register c1 (tmc1)
hd404669 series 65 timer mode register c2 (tmc2: $014): timer mode register c2 (tmc2: $014) is a 3-bit read/write register, used to switch the function of the r31/toc pin and select the timer c output mode as shown in figure 44. timer mode register c2 (tmc2: $014) is reset to $0 by an mcu reset or in stop mode. bit initial value read/write bit name 3 not used 2 0 r/w tmc22 0 0 r/w tmc20 1 0 r/w tmc21 timer mode register c2 (tmc2: $014) tmc22 0 tmc21 r3 1 /toc mode selection r3 1 toc toc toc toc r3 1 port toggle output 0 output 1 output not used pwm output tmc20 0 1 0 1 0 1 0 1 0 1 10 1 figure 44 timer mode register c2 (tmc2) timer write register c (twcl: $00e, twcu: $00f): timer write register c (twcl: $00e, twcu: $00f) is a write-only register composed of a lower digit (twcl: $00e) and an upper digit (twcu: $00f). the lower digit (twcl) of timer write register c is reset to $0 by an mcu reset or in stop mode, while the upper digit (twcu) is undetermined. timer c can be initialized by writing to timer write register c (twcl, twcu). to write the data, first write the lower digit (twcl). the lower digit write does not change the timer c value. next, write the upper digit (twcu). timer c is then initialized to the timer write register c (twcl, twcu) value. when writing to timer write register c (twcl, twcu) from the second time onward, if it is not necessary to change the lower digit (twcl) reload value, timer c initialization is completed by the upper digit write alone.
hd404669 series 66 bit initial value read/write bit name 3 0 w twcl3 2 0 w twcl2 0 0 w twcl0 1 0 w twcl1 timer write register c (lower digit) (twcl: $00e) figure 45 timer write register c lower digit (twcl) bit initial value read/write bit name 3 undefined w twcu3 2 undefined w twcu2 0 undefined w twcu0 1 undefined w twcu1 timer write register c (upper digit) (twcu: $00f) figure 46 timer write register c upper digit (twcu) timer read register c (trcl: $00e, trcu: $00f): timer read register c (trcl: $00e, trcu: $00f) is a read-only register composed of a lower digit (trcl: $00e), and an upper digit (trcu: $00f) from which the value of the upper digit of timer c is read directly. first, read the upper digit (trcu) of timer read register c. the current value of the timer c upper digit is read and, at the same time, the value of the timer c lower digit is latched in the lower digit (trcl) of timer read register c. the timer c value is obtained when the upper digit (trcu) of timer read register c is read by reading the lower digit (trcl) of timer read register c. bit initial value read/write bit name 3 undefined r trcl3 2 undefined r trcl2 0 undefined r trcl0 1 undefined r trcl1 timer read register c (lower digit) (trcl: $00e) figure 47 timer read register c lower digit (trcl)
hd404669 series 67 bit initial value read/write bit name 3 undefined r trcu3 2 undefined r trcu2 0 undefined r trcu0 1 undefined r trcu1 timer read register c (upper digit) (trcu: $00f) figure 48 timer read register c upper digit (trcu) timer d timer d functions: timer d has the following functions. free-running/reload timer external event counter timer output operation (toggle, low-level, high-level, and pwm outputs) input capture timer the block diagram for each operation mode of timer d is shown in figures 49(1) and 49(2).
hd404669 series 68 edge detection logic system clock edge detection control timer mode register d1 (tmd1) timer write register d (twdl) (twdu) 2 4 8 32 128 512 2048 per 2 3 4 4 4 evnd data bus clock line signal line edge detection select register 2 (esr2) timer d interrupt request flag (iftd) timer read register du (trdu) (tcdl) (tcdu) timer mode register d2 (tmd2) timer output control logic tod timer counter d timer read register dl (trdl) prescaler s (pss) free-running/reload control internal data bus selector clock overflow figure 49(1) block diagram of timer d (free-running/reload timer/event counter modes)
hd404669 series 69 edge detection logic system clock edge detection control timer mode register d1 (tmd1) timer read register d (trdl) (trdu) 2 4 8 32 128 512 2048 input capture timer control ? per 2 3 4 4 evnd data bus clock line signal line edge detection select register 2 (esr2) timer counter d (tcdl) (tcdu) timer d interrupt request flag (iftd) error control logic input capture error flag (icef) input capture status flag (icsf) timer mode register d2 (tmd2) read signal prescaler s (pss) selector internal data bus overflow clock figure 49(2) block diagram of timer d (input capture timer)
hd404669 series 70 timer d operations: free-running/reload timer operation: the free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register d1 (tmd1: $010). timer d is initialized to the value set in timer write register d (twdl: $011, twdu: $012) by software and incremented by one at each clock input. if an input clock is applied to timer d after it has reached $ff, an overflow is generated. in this case, if the reload timer function is enabled, timer d is initialized to its initial value set in timer write register d (twdl: $011, twdu: $012); if the free- running timer function is enabled, the timer is initialized to $00 and then incremented again. the timer d interrupt request flag (iftd: $003, 0) is reset by the program, and by an mcu reset or a transition to stop mode. for details, see figure 3, configuration of interrupt control bits and register flag areas, and table 1, initial values after mcu reset. external event counter operation: when external event input is designated for the input clock by timer mode register d1 (tmd1), timer d operates as an external event counter.in this case, pin r4 0 /evnd must be set to evnd by port mode register c (pmrc: $025). either falling or rising edge, or both falling and rising edges of input signals can be selected as the external event detection edge by detection edge select register 2 (esr2: $027). when both rising and falling edges detection is selected, the time between the falling edge and rising edge of input signals must be 2t cyc or longer. timer d is incremented by one at each detection edge selected by detection edge select register 2 (esr2: $027). the other operation is basically the same as the free-running/reload timer operation. timer output operation: the following four output modes can be selected for timer d by setting timer mode register d2 (tmd2: $015). toggle low-level output hige-level output pwm output pin r3 2 /tod is set to tod. ? toggle output: the operation is basically the same as that of timer-c? toggle output. ? 0 output: the operation is basically the same as that of timer-c? 0 output. ? 1 output: the operation is basically the same as that of timer-c? 1 output. ? pwm output: the operation is basically the same as that of timer-c? pwm output.
hd404669 series 71 input capture timer operation: the input capture timer counts the clock cycles between trigger edges input to pin evnd. either falling or rising edge, or both falling and rising edges of input signals can be selected as the trigger input edge by detection edge select register 2 (esr2: $027). when a trigger edge is input to evnd, the count of timer d is written to timer read register d (trdl: $011, trdu: $012), and the timer d interrupt request flag (iftd: $003, bit 0) and the input capture status flag (icsf: $021, bit 0) are set. timer d is reset to $00, and then incremented again. while icsf is set, if a trigger input edge is applied to timer d, or if timer d generates an overflow, the input capture error flag (icef: $021, bit 0) is set. icsf and icef are reset to 0 by mcu reset or by writing 0. by selecting the input capture operation, pin r3 2 /tod is set to r3 2 and timer d is reset to $00. registers for timer d operation: by using the following registers, timer d operation modes are selected and the timer d count is read and written. timer mode register d1 (tmd1: $010) timer mode register d2 (tmd2: $015) timer write register d (twdl: $011, twdu: $012) timer read register d (trdl: $011, trdu: $012) port mode register c (pmrc: $025) detection edge select register 2 (esr2: $027) timer mode register d1 (tmd1: $010): four-bit write-only register that selects the free-running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 50. timer mode register d1 (tmd1: $010) is reset to $0 by an mcu reset or in stop mode. writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register d1 (tmd1: $010) write instruction. setting timer d? initialization by writing to timer write register d (twdl: $011, twdu: $012) must be done after a mode change becomes valid. when selecting the input capture timer operation, select the internal clock as the input clock source. when designating external event input for the input clock, set bit 1 (pmrc1) of port mode register c (pmrc) to 1.
hd404669 series 72 bit initial value read/write bit name 3 0 w tmd13 2 0 w tmd12 0 0 w tmd10 1 0 w tmd11 timer mode register d1 (tmd1: $010) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2048t cyc 512t cyc 128t cyc 32t cyc 8t cyc 4t cyc 2t cyc tmd12 tmd10 tmd11 input clock period and input clock source evnd (external event input) tmd13 0 1 free-running/reload timer selection free-running timer reload timer figure 50 timer mode register d1 (tmd1)
hd404669 series 73 timer mode register d2 (tmd2: $015): timer mode register d2 (tmd2: $015) is a 4-bit read/write register, used to switch the function of the r3 2 /tod pin and select the timer d output mode as shown in figure 51. timer mode register d2 (tmd2: $015) is reset to $0 by an mcu reset and in stop mode. bit initial value read/write bit name 3 0 r/w tmd23 2 0 r/w tmd22 0 0 r/w tmd20 1 0 r/w tmd21 timer mode register d2 (tmd2: $015) tmd22 tmd20 0 1 0 1 0 1 0 1 tmd21 0 1 0 1 0 1 r3 2 /tod mode selection r3 2 tod tod tod tod r3 2 r3 2 port toggle output 0 output 1 output not used pwm output input capture (r3 2 port) tmd23 0 1 : don? care figure 51 timer mode register d2 (tmd2) timer write register d (twdl: $011, twdu: $012): write-only register consisting of the lower digit (twdl: $011) and the upper digit (twdu: $012). the operation of timer write register d is basically the same as that of timer write register c (twcl: $00e, twcu: $00f). bit initial value read/write bit name 3 0 w twdl3 2 0 w twdl2 0 0 w twdl0 1 0 w twdl1 timer write register d (lower digit) (twdl: $011) figure 52 timer write register d lower digit (twdl)
hd404669 series 74 bit initial value read/write bit name 3 undefined w twdu3 2 undefined w twdu2 0 undefined w twdu0 1 undefined w twdu1 timer write register d (upper digit) (twdu: $012) figure 53 timer write register d upper digit (twdu) timer read register d (trdl: $011, trdu: $012): read-only register consisting of the lower digit (trdl) and the upper digit (trdu). the operation of timer read register d is basically the same as that of timer read registerc (trcl: $00e, trcu: $00f). when the input capture timer operation is selected and if the count of timer d is read after a trigger is input, either the lower or upper digit can be read first. bit initial value read/write bit name 3 undefined r trdl3 2 undefined r trdl2 0 undefined r trdl0 1 undefined r trdl1 timer read register d (lower digit) (trdl: $011) figure 54 timer read register d lower digit (trdl) bit initial value read/write bit name 3 undefined r trdu3 2 undefined r trdu2 0 undefined r trdu0 timer read register d (upper digit) (trdu: $012) 1 undefined r trdu1 figure 55 timer read register d upper digit (trdu)
hd404669 series 75 port mode register c (pmrc: $025): write-only register that selects r4 0 /evnd pin function as shown in figure 56. it is reset to $0 by mcu reset. port mode register c (pmrc: $025) bits 3 and 1 (pmrc3, pmrc1) are reset to 00 by an mcu reset or in stop mode. bit 2 (pmrc2) is reset to 0 by an mcu reset, but retains its previous setting in stop mode. port mode register c (pmrc: $025) pmrc3 d 13 / int 0 pin mode selection d 13 int 0 0 1 pmrc2 d 12 / stopc pin mode selection d 12 stopc 0 1 pmrc1 r4 0 /evnd pin mode selection r4 0 evnd 0 1 bit initial value read/write bit name 3 0 w pmrc3 2 0 w pmrc2 0 not used 1 0 w pmrc1 figure 56 port mode register c (pmrc)
hd404669 series 76 detection edge select register 2 (esr2: $027): write-only register that selects the detection edge of signals input to pin evnd as shown in figure 57. it is reset to $0 by an mcu reset or in stop mode. bit initial value read/write bit name 3 0 w esr23 2 0 w esr22 0 0 w esr20 1 0 w esr21 detection edge select register 2 (esr2: $027) esr21 0 1 esr20 0 1 0 1 int 4 detection edge no detection falling-edge detection rising-edge detection double-edge detection esr23 0 1 esr22 0 1 0 1 evnd detection edge no detection falling-edge detection rising-edge detection double-edge detection note: both falling and rising edges are detected. ** * figure 57 detection edge select register 2 (esr2)
hd404669 series 77 serial interface serial interface overview function ?8-bit serial data transmission/reception features multiple transmit clock sources ? external clock ? internal prescaler output clock ? system clock high/low control in idle states configuration serial data register 1 (sr1l: $006, sr1u: $007) serial mode register 1 a (sm1a: $005) serial mode register 1 b (sm1b: $028) port mode register a (pmra: $004) miscellaneous register (mis: $00c) octal counter (oc1) selector the block diagram of the serial interface is shown in figure 58.
hd404669 series 78 2 8 32 128 i/o control logic idle control logic octal counter (oc1) serial 1 interrupt request flag (ifs1) clock serial data register 1 (sr1l, sr1u) serial mode register 1a (sm1a) serial mode register 1b (sm1b) so 1 sck 1 si 1 system clock ? per 512 2048 1/2 data bus clock line signal line 1/2 transfer control prescaler s (pss) internal data bus selector selector figure 58 block diagram of serial interface
hd404669 series 79 serial interface operation selecting and changing the operating mode: table 19 lists the serial interface? operating modes. to select an operating mode, use one of these combinations of port mode register a (pmra: $004) and serial mode register 1a (sm1a: $005) settings; to change the operating mode, always initialize the serial interface internally by writing data to serial mode register 1a (sm1a: $005). note that the serial interface is initialized by writing data to serial mode register 1a(sm1a: $005). refer to the following serial mode register 1a section for details. pin setting: the r4 1 / sck 1 pin is controlled by writing data to serial mode register 1a (sm1a: $005). the r4 2 /si 1 and r4 3 /so 1 pins are controlled by writing data to port mode register a (pmra: $004). refer to the following registers for serial interface section for details. transmit clock source setting: the transmit clock source is set by writing data to serial mode register 1a (sm1a: $005) and serial mode register 1b (sm1b: $028). refer to the following registers for serial interface section for details. data setting: transmit data is set by writing data to the serial data register 1 (sr1l: $006, sr1u: $007). receive data is obtained by reading the contents of the serial data register 1 (sr1l: $006, sr1u: $007). the serial data is shifted by the transmit clock and is input from or output to an external system. the output level of the so 1 pin is invalid until the first data is output after mcu reset, or until the high/low level control in idle states is performed. table 19 serial interface operating modes sm1a pmra bit 3 bit 1 bit 0 operating mode 1 0 0 serial clock continuous output mode 1 transmit mode 1 0 receive mode 1 transmit/receive mode transfer control: the serial interface is activated by the sts instruction. the octal counter is reset to 000 by this instruction, and it increments at the rising edge of the transmit clock. when the eighth transmit clock signal is input or when serial transmission/receive is discontinued, the octal counter is reset to 000, the serial 1 interrupt request flag (ifs1: $003, bit 2) is set, and the transfer stops. when the prescaler output is selected as the transmit clock, the transmit clock frequency is selected as 4t cyc to 8192t cyc by setting bits 2 to 0 (sm1a2?sm1a0) of serial mode register 1a (sm1a: $005) and bit 0 (sm1b0) of serial mode register 1b (sm1b: $028) as listed in table 20.
hd404669 series 80 table 20 serial transmit clock (prescaler output) sm1b sm1a bit 0 bit 2 bit 1 bit 0 transmit clock division ratio transmit clock frequency 0000( per / 2048) ? 2 4096t cyc 1( per / 512) ? 2 1024t cyc 10( per / 128) ? 2 256t cyc 1( per / 32) ? 2 64t cyc 100( per / 8) ? 2 16t cyc 1( per / 2) ? 24t cyc 1000( per / 2048) ? 4 8192t cyc 1( per / 512) ? 4 2048t cyc 10( per / 128) ? 4 512t cyc 1( per / 32) ? 4 128t cyc 100( per / 8) ? 4 32t cyc 1( per / 2) ? 48t cyc operating states: the serial interface has the operating states shown in figure 59 in external clock mode and internal clock mode. sts wait state transmit clock wait state transfer state serial clock continuous output state (internal clock mode only) sts wait state: the serial interface enters sts wait state by mcu reset (00, 10 in figure 59). in sts wait state, the serial interface is initialized and the transmit clock is ignored. if the sts instruction is then executed (01, 11), the serial interface enters transmit clock wait state.
hd404669 series 81 sts wait state (octal counter 1 = 000, transmit clock disabled) transmit clock wait state (octal counter 1 = 000) transfer state (octal counter 1 = 000) mcu reset 00 sm1a write 04 sts instruction 01 transmit clock 02 8 transmit clocks 03 sts instruction (ifs1 1) 05 ? sm1a write (ifs1 1) 06 ? external clock mode sts wait state (octal counter 1 = 000, transmit clock disabled) transmit clock wait state (octal counter 1 = 000) transfer state (octal counter 1 = 000) sm1a write 14 sts instruction 11 transmit clock 12 15 sts instruction (ifs1 1) ? 8 transmit clocks 13 internal clock mode continuous clock output state (pmra 0, 1 = 00) sm1a write 18 transmit clock 17 16 note: refer to the operating states section for the corresponding encircled numbers. mcu reset 10 ? sm1a write (ifs1 1) figure 59 serial interface state transitions transmit clock wait state: transmit clock wait state is between the sts execution and the falling edge of the first transmit clock. in transmit clock wait state, input of the transmit clock (02, 12) increments the octal counter, shifts the serial data register 1 (sr1l: $006, sr1u: $007), and enters the serial interface in transfer state. however, note that if continuous clock output mode is selected in internal clock mode, the serial interface does not enter transfer state but enters continuous clock output state (17). the serial interface enters sts wait state by writing data to serial mode register 1a (sm1a: $005) (04, 14) in transmit clock wait state. transfer state: transfer state is between the falling edge of the first clock and the rising edge of the eighth clock. in transfer state, the input of eight clocks or the execution of the sts instruction sets the octal counter to 000, and the serial interface enters another state. when the sts instruction is executed (05, 15), transmit clock wait state is entered. when eight clocks are input, transmit clock wait state is entered (03) in external clock mode, and sts wait state is entered (13) in internal clock mode. in internal clock mode, the transmit clock stops after outputting eight clocks. in transfer state, writing data to serial mode register 1a (sm1a: $005) (06, 16) initializes the serial interface, and sts wait state is entered.
hd404669 series 82 if the state changes from transfer to another state, the serial 1 interrupt request flag (ifs1: $003, bit 2) is set by the octal counter that is reset to 000. continuous clock output state (only in internal clock mode): continuous clock output state is entered only in internal clock mode. in this state, the serial interface does not transmit/receive data but only outputs the transmit clock from the sck 1 pin. when bits 1 and 0 (pmra1, pmra0) of port mode register a (pmra: $004) are 00 in transmit clock wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state. if serial mode register 1a (sm1a: $005) is written to in continuous clock output mode (18), sts wait state is entered. high/low control in idle states: in idle states, that is, sts wait state and transmit clock wait state, the output level of the so 1 pin can be controlled by setting bit 1 (sm1b1) of serial mode register 1b (sm1b: $028) to 0 or 1. the high/low control example is shown in figure 60. note that the high/low level cannot be controlled in transfer state.
hd404669 series 83
state mcu reset pmra write sm1a write sm1b write sr1l, sr1u write sts instruction sck 1 pin (input) so 1 pin ifs1 idle idle idle idle sts wait state transmit clock wait state transfer state transmit clock wait state sts wait state port selection external clock selection output level control in idle states dummy write for state transition output level control in idle states data write for transmission undefined lsb msb flag reset at transfer completion external clock mode state mcu reset pmra write sm1a write sm1b write sr1l, sr1u write sts instruction sck 1 pin (output) so 1 pin ifs1 sts wait state transfer state transmit clock wait state sts wait state port selection internal clock selection output level control in idle states data write for transmission output level control in idle states undefined lsb msb flag reset at transfer completion internal clock mode figure 60 example of serial interface operation sequence
hd404669 series 84 transmit clock error detection (in external clock mode): the serial interface will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. a transmit clock error of this type can be detected as shown in figure 61. if more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse by noise, the octal counter reaches 000, the serial 1 interrupt request flag (ifs1: $003, bit 2) is set, and transmit clock wait state is entered. at the falling edge of the next normal clock signal, the transfer state is entered. meanwhile, in the interrupt handling routine, transfer end processing is performed, the serial 1 interrupt request flag is reset, and a dummy write is performed to serial mode register 1a (sm1a: $005). the serial interface then returns to the sts wait state, and the serial 1 interrupt request flag (ifs1: $003, 2) is set again. it is therefore possible to detect a serial clock error by testing the serial 1 interrupt request flag after the dummy write to serial mode register 1a.
hd404669 series 85 transfer completion (ifs1 1) interrupts inhibited ifs1 0 sm1a write ifs1 = 1? transmit clock error processing normal termination ? ? yes no transmit clock error detection flowchart transmit clock error detection procedure state sck 1 pin (input) transmit clock wait state transfer state transfer state transmit clock wait state noise transfer state has been entered by the transmit clock error. when sm1a is written, ifs1 is set. flag set because octal counter reaches 000 flag reset at transfer completion sm1a write ifs1 12 3 45678 figure 61 transmit clock error detection
hd404669 series 86 notes on use: initialization after writing to registers: if port mode register a (pmra: $004) is written to in transmit clock wait state or in transfer state, the serial interface must be initialized by writing to serial mode register 1a (sm1a: $005) again. serial 1 interrupt request flag (ifs1: $003, bit 2) set: if the state is changed from transfer to another by writing to serial mode register 1a (sm1a: $005) or executing the sts instruction during the first low pulse of the transmit clock, the serial interrupt request flag 1 (ifs1: $003, 2) is not set. to set the serial interrupt request flag, serial mode register 1a (sm1a: $005) write or sts instruction execution must be programmed to be executed after confirming that the sck 1 pin is at 1, that is, after executing the input instruction to port r4. registers for serial interface the serial interface operation is selected, and serial data is read and written by the following registers. serial mode register 1a (sm1a: $005) serial mode register 1b (sm1b: $028) serial data register 1 (sr1l: $006, sr1u: $007) port mode register a (pmra: $004) miscellaneous register (mis: $00c) serial mode register 1a (sm1a: $005): this register has the following functions (figure 62). r4 1 / sck 1 pin function selection transfer clock selection prescaler division ratio selection serial interface initialization serial mode register 1a (sm1a: $005) is a 4-bit write-only register. it is reset to $0 by an mcu reset or when the mcu switches to stop mode. a write signal input to serial mode register 1a (sm1a: $005) discontinues the input of the transmit clock to the serial data register 1 (sr1l: $006, sr1u: $007) and octal counter, and the octal counter is reset to 000. therefore, if a write is performed during data transfer, the serial 1 interrupt request flag (ifs1: $003, bit 2) is set. written data is valid from the second instruction execution cycle after the write operation, so the sts instruction must be executed at least two cycles after that.
hd404669 series 87 bit initial value read/write bit name 3 0 w sm1a3 2 0 w sm1a2 0 0 w sm1a0 1 0 w sm1a1 serial mode register 1a (sm1a: $005) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 sm1a2 sm1a0 sm1a1 sm1a3 0 1 r4 11 1 / sck mode selection r4 1 1 sck output output input clock source prescaler division ratio refer to table 20 sck prescaler system clock external clock figure 62 serial mode register 1a (sm1a) serial mode register 1b (sm1b: $028): this register has the following functions (figure 63). serial clock division ratio selection high/low level control in idle states serial mode register 1b (sm1b: $028) is a 2-bit write-only register. it cannot be written during data transfer. setting bit 0 (sm1b0) of the serial mode register 1b (sm1b: $028) selects the divisor applied to the prescaler output used for the transfer clock. only bit 0 (sm1b0) is cleared to 0 by an mcu reset or when the mcu switches to stop mode. bit 1 (sm1b1) of the serial mode register (sm1b: $028) controls the high/low state of the so 1 pin during idle. the so 1 pin changes state as soon as the high/low control bit is written. the value of this bit is undefined after a reset or when the mcu enters stop mode.
hd404669 series 88 bit initial value read/write bit name 3 not used 2 not used 0 0 w sm1b0 1 undefined w sm1b1 sm1b0 0 1 transmit clock division ratio prescaler output divided by 2 prescaler output divided by 4 serial mode register 1b (sm1b: $028) sm1b1 0 1 output level control in idle states low level high level figure 63 serial mode register 1b (sm1b) serial data register 1 (sr1l: $006, sr1u: $007): this register has the following functions (figures 64 and 65). transmission data write and shift receive data shift and read writing data in this register is output from the so 1 pin, lsb first, synchronously with the falling edge of the transmit clock; data is input, lsb first, through the si 1 pin at the rising edge of the transmit clock. input/output timing is shown in figure 66. data cannot be read or written during serial data transfer. if a read/write occurs during transfer, the accuracy of the resultant data cannot be guaranteed. bit initial value read/write bit name 3 undefined r/w sr1l3 2 undefined r/w sr1l2 0 undefined r/w sr1l0 1 undefined r/w sr1l1 serial data register 1 (lower digit) (sr1l: $006) figure 64 serial data register 1 (sr1l) bit initial value read/write bit name 3 undefined r/w sr1u3 2 undefined r/w sr1u2 0 undefined r/w sr1u0 1 undefined r/w sr1u1 serial data register 1 (upper digit) (sr1u: $007) figure 65 serial data register 1 (sr1u)
hd404669 series 89 lsb msb 12 345 678 transmit clock serial output data serial input data latch timing figure 66 serial interface output timing port mode register a (pmra: $004): this register has the following functions (figure 67). r4 2 /si 1 pin function selection r4 3 /so 1 pin function selection port mode register a (pmra: $004) is a 2-bit write-only register. it is reset to "--00" by an mcu reset or when the mcu switches to stop mode. bit initial value read/write bit name 3 not used 2 not used 0 0 w pmra0 1 0 w pmra1 pmra0 0 1 r4 3 /so 1 mode selection r4 3 1 so port mode register a (pmra: $004) pmra1 0 1 r4 2 /si 1 mode selection r4 2 si 1 figure 67 port mode register a (pmra)
hd404669 series 90 miscellaneous register (mis: $00c): this register has the following function (figure 68). r4 3 /so 1 pin pmos control miscellaneous register (mis: $00c) is a 4-bit write-only register and is reset to $0 by an mcu reset or in stop mode. bit initial value read/write bit name note: * the value is applied only when direct transfer operation is used. 3 0 w mis3 2 0 w mis2 0 0 w mis0 1 0 w mis1 miscellaneous register (mis: $00c) mis1 0 1 mis0 0 1 0 1 t rc 0.12207 ms 0.24414 ms * 7.8125 ms 31.25 ms not used mis2 0 1 r4 31 /so pmos control on off mis3 0 1 pull-up/pull-down mos control off on figure 68 miscellaneous register (mis)
hd404669 series 91 dtmf generation circuit the mcu provides a dual-tone multifrequency (dtmf) generation circuit. figure 69 shows a block diagram of the dtmf circuit. a dtmf signal consists of two sine waves corresponding to the numbers and symbols on a telephone keypad. dtmf signals are used to access telephone switching equipment. figure 70 shows the dtmf frequency matrix. the osc clock (400 khz, 800 khz, 2 mhz, 3.58 mhz, 4 mhz, 7.16 mhz, or 8 mhz) is changed into seven clock signals through the division circuit (1/2, 1/5, 1/9*, 1/10, 1/18*, and 1/20). the dtmf circuit uses one of the seven clock signals, which is selected by the system clock select register 1, 2 (ssr1: $029, ssr2: $02a) depending on the osc clock frequency. the dtmf circuit has transformed programmable dividers, sine wave counters, and control registers. the dtmf generation circuit is controlled by the following three registers.
hd404669 series 92 sine wave counter d/a transformation program divider feedback sine wave counter d/a transformation program divider feedback toner vt ref tonec toner output control tonec output control 1/2 1/5 1/9 * f osc tone generator control register (tgc) system clock select register 1 (ssr1) system clock select register 2 (ssr2) 400 khz * 2 2 2 tone generator mode register (tgm) 2 data bus clock line internal data bus 1/10 1/18 * 1/20 note: * 397.8 khz when an f osc frequency of 3.58 mhz or 7.16 mhz is used. signal line selector figure 69 block diagram of dtmf circuit
hd404669 series 93 123a 456b 789c 0#d r1 (697hz) r2 (770hz) r3 (852hz) r4 (941hz) c1 (1,209hz) c2 (1,336hz) c3 (1,477hz) c4 (1,633hz) figure 70 dtmf keypad and frequencies tone generator mode register (tgm: $019): the tone generator mode register (tgm: $019) is a 4-bit write-only register that controls the generated dtmf frequencies as shown in figure 71. tgm is initialized to $0 by an mcu reset or in stop mode, watch mode, and subactive mode. bit initial value read/write bit name 3 0 w tgm3 2 0 w tgm2 0 0 w tgm0 1 0 w tgm1 tone generator mode register (tgm: $019) tgm3 0 0 1 1 tgm2 0 1 0 1 tonec output frequencies c1 (1,209 hz) c2 (1,336 hz) c3 (1,477 hz) c4 (1,633 hz) tgm1 0 0 1 1 tgm0 0 1 0 1 toner output frequencies r1 (697 hz) r2 (770 hz) r3 (852 hz) r4 (941 hz) figure 71 tone generator mode register (tgm)
hd404669 series 94 tone generator control register (tgc: $01a): the tone generator control register (tgc: $01a) is a 3- bit write-only register that controls starting and stopping of dtmf signal generation as shown in figure 72. tgc is initialized to 000- by an mcu reset or in stop mode, watch mode, or subactive mode. tonec output and toner output are controlled individually by tgc3 and tgc2, and overall dtmf control is performed by tgc1. bit initial value read/write bit name 3 0 w tgc3 2 0 w tgc2 0 not used 1 0 w tgc1 tone generator control register (tgc: $01a) tgc1 0 1 dtmf enable bit dtmf disable dtmf enable tgc2 0 1 toner output control (row) no output toner output (active) tgc3 0 1 tonec output control (column) no output tonec output (active) figure 72 tone generator control register (tgc) system clock select registers 1 and 2 (ssr1: $029 and ssr2: $02a): the system clock select registers 1 and 2 (ssr1: $029 and ssr2: $02a) are 4-bit write-only registers. applications must set these registers to the values shown in figure 73 that correspond to the frequency of the oscillator circuit connected to the osc 1 and osc 2 pins. if the oscillator frequency and the system clock select register settings differ from the combination shown in figure 73, the dtmf output frequencies will not have the correct values as shown in figure 71. except for the ssr13 bit, the system clock select registers 1 and 2 (ssr1: $029 and ssr2: $02a) are initialized to $0 by an mcu reset or when the mcu switches to stop mode.
hd404669 series 95 ssr23 system clock selection 0 400khz 800 khz 2 mhz 4 mhz system clock select register 1 (ssr1: $029) ssr22 0 ssr11 0 1 ssr10 0 1 0 1 3.58 mhz 1 1 8 mhz 011 7.16 mhz 1 : don't care ssr12 0 1 32 khz division ratio switch f sub =f x /8 f sub =f x /4 ssr13 0 1 32 khz oscillation stop setting oscillation continues in stop mode oscillation stops in stop mode ssr21 system clock division ratio selection * 2 0 1 division by 4 division by 8 division by 16 division by 32 system clock select register 2 (ssr2: $02a) ssr20 0 1 0 1 bit initial value read/write bit name 3 0 w ssr13 * 1 2 0 w ssr12 0 0 w ssr10 1 0 w ssr11 bit initial value read/write bit name 3 0 w ssr23 2 0 w ssr22 0 0 w ssr20 1 0 w ssr21 1. ssr13 is cleared to 0 only by reset input. in the case of stopc input in stop mode it retains its current value. ssr13 is not reset in stop mode 2. the dtmf generation circuit frequencies are not affected by the system clock division ratio settin g . notes: figure 73 system clock select register 1 and 2 (ssr1, ssr2)
hd404669 series 96 dtmf output: the sine waves of the row-group and column-group are output from the dtmf output pins (toner and tonec). these are output by a high-precision resistance-ladder type d/a converter. figure 74 shows the tone output pin equivalent circuit, and figure 75 shows the output waveform. one output waveform cycle is composed of 32 slots, giving stable output with a low distortion factor. table 21 shows the deviation of the output frequencies with respect to the standard dtmf signals. table 21 frequency deviation of the mcu from standard dtmf ( f osc =400khz , 800khz , 2mhz , 4mhz , 8mhz ) standard dtmf (hz) mcu (hz) deviation from standard (%) r1 697 694.44 ?.37 r2 770 769.23 ?.10 r3 852 851.06 ?.11 r4 941 938.97 ?.22 c1 1,209 1,212.12 0.26 c2 1,336 1,333.33 ?.20 c3 1,477 1,481.48 0.30 c4 1,633 1,639.34 0.39 table 22 frequency deviation of the mcu from standard dtmf ( f osc =3.58khz , 7.16mhz ) standard dtmf (hz) mcu (hz) deviation from standard (%) r1 697 690.58 ?.92 r2 770 764.96 ?.65 r3 852 846.33 ?.67 r4 941 933.75 ?.77 c1 1,209 1,205.39 ?.30 c2 1,336 1,325.92 ?.75 c3 1,477 1,473.25 ?.25 c4 1,633 1,630.23 ?.17 notes: 1. the dtmf signal frequency deviation must be within 1.5%, totaling the values in tables 21 and 22 and the precision of the oscillator used. when an f osc frequency of 3.58 mhz or 7.16 mhz is used, in particular, the frequency deviation is greater (max - 0.92%) than with an f osc frequency of 400 khz, 800 khz, 2 mhz, 4 mhz, or 8 mhz, and thorough consultation with the oscillator manufacturer is essential before deciding on the oscillator to be used. 2. this frequency deviation does not include the frequency deviation of the oscillator. also, the ratio of oscillator waveform high-level width and low-level width in this case is 50% : 50%.
hd404669 series 97 vt ref gnd switch control toner tonec figure 74 tone output equivalent circuit vt ref gnd 12345678910111213141516171819202122232425262728293031 32 time slots figure 75 waveform of tone output
hd404669 series 98 comparator the mcu has a built-in comparator that compare an input voltage with the reference voltage (v cref ). the comparator block diagram is shown in figure 76. the comparator can operate in active mode and subactive mode. they are halted in other modes. 2 compare enable register (cer) compare data register (cdr) comp 0 comp 1 vc ref comparator - + selector internal data bus figure 76 comparator block diagram comparator operation (1) analog input pin selection is performed by bits 0 and 1 (cer0, cer1) of the compare enable register (cer). setting bit 3 (cer3) to 1 places the rd 0 /comp 0 and rd 1 /comp 1 pins in analog input mode and starts comparator operation. while comparator operation is in progress, none of these pins (including pins not used for comparison) can be used as r port pins. (2) the compare result can be read by means of a bit test instruction (tm or tmd) on the compare data register (cdr) bit corresponding to the selected analog input pin.
hd404669 series 99 registers used by comparator compare enable register (cer: $018) compare data register (cdr: $017) compare enable register (cer: $018): the compare enable register (cer) is a 3-bit write-only register that selects comparator operation and the analog input pin (figure 77). cer is reset by an mcu reset or in stop mode. analog input pin selection comp 0 comp 1 not used compare enable register (cer: $018) cer0 0 1 cer1 0 1 : don't care cer3 0 comparator operation selection comparator operation not selected: digital input mode rd 0 /comp 0 and rd 1 /comp 1 pins function as r port pins 1 comparator operation selected: analog input mode rd 0 /comp 0 and rd 1 /comp 1 pins function as comparator pins bit initial value read/write bit name 3 0 w cer3 2 not used 0 0 w cer0 1 0 w cer1 figure 77 compare enable register (cer) compare data register (cdr: $017): the compare data register (cdr) is a 2-bit read-only register that holds the result of the comparison between the analog input pin and the reference voltage (figure 78). when comparator operation is started (cer3 is set to 1), the result of the comparison between the analog input pin selected by the compare enable register (cer) and the reference voltage is read into the corresponding bit of the compare data register (cdr). the value of the other bits in cdr is undetermined. the cdr value is not retained after the comparator operation (when cer3 = 0), and is undetermined except during comparator operation.
hd404669 series 100 cdr 0 0 1 result of comparison between comp 0 pin and reference voltage comp 0 pin < reference voltage comp 0 pin > reference voltage compare data register (cdr: $017) cdr1 0 1 result of comparison between comp 1 pin and reference voltage comp 1 pin < reference voltage comp 1 pin > reference voltage bit initial value read/write bit name 3 not used 2 not used 0 undetermined r cdr0 1 undetermined r cdr1 figure 78 compare data register (cdr)
hd404669 series 101 ztat tm microcomputer with built-in programmable rom 1. precautions for use of ztat tm microcomputer with built-in programmable rom (1) precautions for writing to programmable rom built in ztat tm microcomputer in the ztat tm microcomputer with built-in plastic mold one-time programmable rom, incomplete electrical connection between the prom writer and socket adapter causes writing errors and, makes the computer unoperatable. to enhance the writing efficiency, attention should be paid to the following points: (a) make sure that the socket adapter is firmly fixed to the prom writer and connected electrically with each other (neither opened nor shorted), before starting the writing process. (b) to secure the electrical connection between the contact pin and ic lead, make sure that there is no foreign substance on the contact pin of the socket adapter, which may cause improper electrical connection. (c) when inserting the ic, be careful to protect the ic lead from bending in order to secure the electrical connection between the contact pin and ic lead. if the lead is bent, correct the bending and insert it again. (d) if any trouble is noticed during a blank check to be performed to prevent erroneous writing due to improper electrical connection, carry out the writing process again according to above steps (a), (b), and (c). (e) during the writing process, do not touch the socket adapter and ic to prevent erroneous writing. (f) to write continuously in the ic, follow steps (a), (b), (c), (d) and (e). (g) if a writing error recurs, or the rate of writing errors occur frequently, stop writing and check the prom writer, socket adapter, etc. for defects. (h) if any problem is noticed in the written program or in the program after being left at a high temperature, consult our technical staff. (2) precautions when new prom writer, socket adapter or ic is used when a new prom writer, socket adapter or ic is employed, breakdown of the ic may occur or its writing may become impossible because the noise, overshoot, timing or other electrical characteristics may be inconsistent with the assured ic writing characteristics. to avoid such troubles, check the following points before starting the writing process. (a) to ensure stable writing operation, check that the v cc of the power supplied to the prom writer, power source current capacity of v pp , and current consumption at the time of writing to ic are provided with sufficient margin. (b) to prevent breakdown of the ic, check that the power source voltage between gnd-v cc and gnd- v pp , and overshoot or undershoot of the power source at the connecting terminal of the socket adapter are within the ratings. particularly, if the overshoot or undershoot exceeds the maximum rating, the pin connection may be damaged, leading to permanent breakdown. if overshoot or undershoot occurs, recheck the power source damping resistance of capacity. (c) to prevent breakdown of the ic and for stable writing and reading operation, insert the ic into the socket adapter and check the power noise between the gnd-v cc and gnd-v pp near the ic connecting
hd404669 series 102 terminal. if power source noise is noticed, insert an appropriate capacitor between the gnd power sources depending on the noise generated. in case of high frequency noise, insert a capacitor of low inductance. (d) for stable writing and reading operation, insert the ic into the socket adapter and check the input waveform, timing and noise near the r/w, cs, address and data terminals. particularly, since recent ics have increased in speed, caution should be exercised against the noise to the power source or address due to crosstalk from the output data terminal. to avoid these problems, inserting a low inductance capacitor between the gnd and power source or inserting a damping resistance to the output data terminal is effective. (e) particularly, when a multiple prom writer is used, perform above items (a), (b), (c), and (d) assuming all ics inserted into the socket adapter. (f) in the case of a multiple prom writer, when an unacceptable result is noticed during a blank check performed to prevent erroneous writing due to improper electrical connection of the power source, etc., rewriting is impossible unless every writing process can be stopped. therefore, the potential increases due to erroneous writing because of improper connection. be sure to check the electrical connection between the prom writer and socket adapter and ic. (g) if any abnormality is noticed while checking a written program, consult our technical staff. 2. programming of built-in programmable rom the mcu can stop its function as an mcu in prom mode for programming the built-in prom. prom mode is set up by setting the test , m 0 , and m 1 terminals to ?ow?level and the reset terminal to ?igh?level. writing and reading specifications of the prom are the same as those for the commercial eprom27256. using a socket adapter for specific use of each product, programming is possible with a general-purpose prom writer. since an instruction of the hmcs400 series is 10 bits long, a conversion circuit is incorporated to adapt the general-purpose prom writer. this circuit splits each instruction into five lower bits and five higher bits to write from or read to two addresses. this enables use of a general-purpose prom. for instance, to write to a 16kword of built-in prom with a general-purpose prom writer, specify 32kbyte address ($0000-$7fff). an example of prom memory map is shown in figure 80. notes: 1. when programming with a prom writer, set up each rom size to the address given in table 24. if it is programmed erroneously to an address given in table 24 or later, check of writing of prom may become impossible. particularly, caution should be exercised in the case of a plastic package since reprogramming is impossible with it. set the data in unused addresses to $ff. 2. if the indexes of the prom writer socket, socket adapter and product are not aligned precisely, the product may break down due to overcurrent. be sure to check that they are properly set to the writer before starting the writing process.
hd404669 series 103 3. two levels of program voltages (v pp ) are available for the prom: 12.5 v and 21 v. our product employs a v pp of 12.5 v. if a voltage of 21 v is applied, permanent breakdown of the product will result. the v pp of 12.5 v is obtained for the prom writer by setting it according to the intel 27256 specifications. writing/verification programming of the built-in program rom employs a high speed programming method. with this method, high speed writing is effected without voltage stress to the device or without damaging the reliability of the written data. a basic programming flow chart is shown in figure81 and a timing chart in figure82. for precautions for prom writing procedure, refer to "ztat tm microcomputer on-chip programmable rom characteristics and usage notes." table 23 selection of mode pins mode ce oe v pp o 0 ? 4 writing ?ow ?igh v pp data input verification ?igh ?ow v pp data output prohibition of programming ?igh ?igh v pp high impedance table 24 prom writer program address rom size address 8k $0000~$3fff 12k $0000~$5fff 16k $0000~$7fff
hd404669 series 104 programmable rom (hd407a4669) the hd407a4669 is a ztat tm microcomputer with built-in prom that can be programmed in prom mode. prom mode pin description pin no. mcu mode prom mode pin no. mcu mode prom mode fp-64a pin name i/o pin name i/o fp-64a pin name i/o pin name i/o 1re 0 /vc ref i33r3 3 i/o 2 test i gnd 34 r3 2 /tod i/o 3 osc 1 iv cc ?5 r3 1 /toc i/o 4 osc 2 o36r4 0 /evnd i/o 5 reset i v cc ?7 r4 1 / sck 1 i/o 6 x1 i gnd 38 r4 2 /si 1 i/o 7 x2 o 39 r4 3 /so 1 i/o 8 gnd gnd 40 r6 0 i/o a 1 i 9d 0 i/o ce i41 r6 1 i/o a 2 i 10 d 1 i/o oe i42 r6 2 i/o a 3 i 11 d 2 i/o v cc ?3 r6 3 i/o a 4 i 12 d 3 i/o v cc ?4 r7 0 i/o o 0 i/o 13 d 4 i/o 45 r7 1 i/o o 1 i/o 14 d 5 i/o 46 r7 2 i/o o 2 i/o 15 d 9 i/o 47 r7 3 i/o o 3 i/o 16 d 10 i/o a 13 i48 r8 0 i/o o 4 i/o 17 d 11 i/o a 14 i49 r8 1 i/o 18 d 12 / stopc ia 9 i50 r8 2 i/o 19 d 13 / int 0 iv pp ?1 r8 3 i/o 20 r0 0 / int 1 i/o gnd 52 r9 0 i/o o 4 i/o 21 r0 1 /int 2 i/o gnd 53 r9 1 i/o o 3 i/o 22 r0 2 /int 3 i/o 54 r9 2 i/o o 2 i/o 23 r0 3 /int 4 i/o 55 r9 3 i/o o 1 i/o 24 r1 0 i/o a 5 i56 ra 0 i/o o 0 i/o 25 r1 1 i/o a 6 i57 ra 1 i/o v cc 26 r1 2 i/o a 7 i 58 sel i 27 r1 3 i/o a 8 i59 v cc ? cc 28 r2 0 i/o a 0 i 60 tonec o 29 r2 1 i/o a 10 i 61 toner o 30 r2 2 i/o a 11 i62 vt ref i 31 r2 3 i/o a 12 i 63 rd0/comp 0 i 32 r3 0 i/o 64 rd1/comp 1 i
hd404669 series 105 notes: 1. i/o: i/o pin, i: input pin, o: output pin 2. as there are two each of pins o 0 to o 4 , the respective pairs should be shorted. 3. unused data pins (o 5 to o 7 ) on the prom programmer side should be handled as shown below on the socket side. v cc o 5 , o 6 , o 7 4. pin a 9 should be handled as shown below on the socket side. v cc a 9 programmer side hd407a4669
hd404669 series 106 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 o 4 o 3 o 2 o 1 o 0 a 4 a 3 a 2 a 1 gnd v cc v cc gnd gnd ce oe v cc v cc a 13 v cc v cc o 0 o 1 o 2 o 3 o 4 a 14 a 9 v pp gnd gnd a 10 a 11 a 12 hd407a4669h fp-64a (top view) a 8 a 0 a 5 a 6 a 7 figure 79 pin arrangement in prom mode
hd404669 series 107 $0000 vector address zero-page subroutine (64 words) pattern (4,096 words) program (16,384 words) $0001 $001f $0080 $007f $2000 $1fff $0020 $7fff bit 4 bit 8 bit 3 bit 7 bit 2 bit 6 bit 1 bit 5 bit 0 bit 9 upper three bits are not to be used (fill them with 111) upper 5 bits lower 5 bits $0000 $000f $0010 $003f $0040 $3fff $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f jmpl instruction (jump to reset, stopc routine) jmpl instruction (jump to int 0 routine) jmpl instruction (jump to timer a routine) jmpl instruction (jump to int 2 routine) jmpl instruction (jump to int 1 routine) jmpl instruction (jump to timer c, int 3 routine) jmpl instruction (jump to timer d, int 4 routine) . . . . . . . . . jmpl instruction (jump to serial 1 routine) $0fff $1000 11 1 11 1 figure 80 memory map in prom mode
hd404669 series 108 start verification ok? set write/verify modes v = 12.5 0.3 v v = 6.0 0.25 v, pp cc address = 0 n = 0 n + 1 n ? program t =1 ms 5% pw program t = 3n ms opw last address? n < 25? yes no no no address + 1 address ? yes set read mode v = 5.0 0.5 v, v = v 0.6 v cc pp cc read all addresses ? end reject no yes yes figure 81 flowchart of high-speed programming
hd404669 series 109 programming electrical characteristics dc characteristics (v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, gnd = 0v, t a = 25 c 5 c, unless otherwise specified) item pin(s) symbol min typ max unit test condition input high voltage level o 0 ? 4 , a 0 ? 14 , oe , ce v ih 2.2 v cc + 0.3 v input low voltage level o 0 ? 4 , a 0 ? 14 , oe , ce v il ?.3 0.8 v output high voltage level o 0 ? 4 v oh 2.4 v i oh = ?00 m a output low voltage level o 0 ? 4 v ol 0.4 v i ol = 1.6 ma input leakage current o 0 ? 4 , a 0 ? 14 , oe , ce ? i il ? 2 m av in = 5.25 v/0.5 v v cc current i cc 30 ma v pp current i pp 40 ma ac characteristics (v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, gnd = 0v, t a = 25 c 5 c, unless otherwise specified) item symbol min typ max unit test condition address setup time t as 2 m s see figure 82 oe setup time t oes 2 m s data setup time t ds 2 m s address hold time t ah 0 m s data hold time t dh 2 m s data output disable time t df 130 ns v pp setup time t vps 2 m s program pulse width t pw 0.95 1.0 1.05 ms ce pulse width during overprogramming t opw 2.85 78.75 ms v cc setup time t vcs 2 m s data output delay time t oe 0 500 ns note: input pulse level: 0.8 v to 2.2 v input rise/fall time: 20 ns input timing reference levels: 1.0 v, 2.0 v output timing reference levels: 0.8 v, 2.0 v
hd404669 series 110 address data v pp v pp gnd gnd v cc v cc ce oe t as t ds t dh t vps t vcs t pw t opw t oes t oe data out valid t df t ah verify write data in stable figure 82 prom write/verify timing
hd404669 series 111 ztat tm microcomputer usage notes ztat tm microcomputer on-chip programmable rom characteristics and useage notes principles of programming/erasure: a memory cell in a ztat tm microcomputer is the same as an eprom cell; it is programmed by applying a high voltage between its control gate and drain to inject hot electrons into its floating gate. these electrons are stable, surrounded by an energy barrier formed by an sio 2 film. the change in threshold voltage of a memory cell with a charged floating gate makes the corresponding bit appear as 0. the charge in a memory cell may decrease with time. this decrease is usually due to one of the following causes: ultraviolet light excites electrons, allowing them to escape. this effect is the basis of the erasure principle. heat excites trapped electrons, allowing them to escape. high voltages between the control gate and drain may erase electrons. if the oxide film covering a floating gate is defective, the electron erasure rate will be greater. however, electron erasure does not often occur because defective devices are detected and removed at the testing stage. control gate floating gate drain sio 2 source nn ++ control gate floating gate drain sio 2 source nn ++ erasure (1) write (0) figure 83 cross-sections of a prom cell prom programming: prom memory cells must be programmed under specific voltage and timing conditions. the higher the programming voltage v pp and the longer the programming pulse t pw is applied, the more electrons are injected into the floating gates. however, if v pp exceeds specifications, the pn junctions may be permanently damaged. pay particular attention to overshooting in the prom programmer. in addition, note that negative voltage noise will produce a parasitic transistor effect that may reduce breakdown voltages. the ztat tm microcomputer is electrically connected to the prom programmer by a socket adapter. therefore, note the following points:
hd404669 series 112 check that the socket adapter is firmly mounted on the prom programmer. do not touch the socket adapter or the lsi during the programming. touching them may affect the quality of the contacts, which will cause programming errors. prom reliability after programming: in general, semiconductor devices retain their reliability, provided that some initial defects can be excluded. these initial defects can be detected and rejected by screening. baking devices under high-temperature conditions is one method of screening that can rapidly eliminate data-hold defects in memory cells. (refer to the previous principles of programming/erasure section.) ztat tm microcomputer devices are extremely reliable because they have been subjected to such a screening method during the wafer fabrication process, but hitachi recommends that each device be exposed to 150 c at one atmosphere after it is programmed, to ensure its best performance. the recommended screening procedure is shown in figure 84. note: exposure time is measured from when the temperature in the heater reaches 150 c. write the program data and verify the values written expose to high temperature, without power 150 c 10 c, 48 h +8 h 0 h * * program read check v = 4.5 v or 5.5 v cc figure 84 recommended screening procedure note: if programming errors occur continuously during prom programming, suspend programming and check for problems in the prom programmer or socket adapter, using a windowed-package microcomputer with on-chip eprom, etc. ..... if programming verification indicates errors in programming or after high-temperature exposure, please inform hitachi. write rate: a write rate of 95% or above is guaranteed.
hd404669 series 113 addressing modes ram addressing modes the mcu has three ram addressing modes, as shown in figure 85 and described below. register indirect addressing mode: the contents of the w, x, and y registers (10 bits in total) are used as a ram address. for $090 to $25f, a bank setting must be made in the bank register (v: $03f). direct addressing mode: a direct addressing instruction consists of two words. the first word contains the opcode, and the contents of the second word (10 bits) are used as a ram address. memory register addressing mode: the memory registers (mr), which are located in 16 addresses from $040 to $04f, are accessed with the lamr and xmra instructions. ap 9 ap 0 w 1 y 0 w register x register y register ram address register indirect addressing ap 9 ap 0 ram address direct addressing d 9 d 0 2nd word of instruction opcode 1st word of instruction ap 9 ap 0 ram address memory register addressing m 3 opcode instruction 000100 ap 8 ap 7 ap ap 5 ap 4 6 ap 3 ap 2 ap 1 ap ap ap ap ap ap ap ap 87654321 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 ap 8 ap 7 ap 6 ap 5 ap 4 ap 3 ap 2 ap 1 w 0 x 3 x 2 x 1 x 0 y 3 y 2 y 1 m 2 m 1 m 0 figure 85 ram addressing modes
hd404669 series 114 rom addressing modes and the p instruction the mcu has four rom addressing modes, as shown in figure 86 and described below. d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 2nd word of instruction opcode 1st word of instruction [jmpl] [brl] [call] pc 9 pc 8 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 pc pc pc pc 10 11 12 13 program counter direct addressing zero page addressing d 5 d 4 d 3 d 2 d 1 d 0 instruction [cal] opcode pc 98 pc 76 pc 54 pc 3 pc 1 pc 0 pc pc 10 11 12 13 program counter 00 00 0 0 0 0 pc pc pc pc pc pc 2 b 1 b 0 a 3 a 2 a 1 a 0 accumulator program counter table data addressing pc 9 pc 8 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 pc pc pc 10 11 12 13 b 2 b 3 b register p 3 p 0 [tbr] instruction opcode 0 0 p 2 p 1 pc opcode b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 instruction pc 90 pc pc pc 11 12 13 program counter current page addressing [br] pc 10 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc pc 8 pc p 0 p 1 p 2 p 3 figure 86 rom addressing modes
hd404669 series 115 direct addressing mode: a program can branch to any address in the rom memory space by executing the jmpl, brl, or call instruction. each of these instructions replaces the 14 program counter bits (pc 13 ?c 0 ) with 14-bit immediate data. current page addressing mode: the mcu has 64 pages of rom with 256 words per page. a program can branch to any address in the current page by executing the br instruction. this instruction replaces the eight low-order bits of the program counter (pc 7 ?c 0 ) with eight-bit immediate data. a branch by a br instruction located at a page boundary differs from other cases: see figure 88. zero-page addressing mode: a program can branch to the zero-page subroutine area located at $0000 $003f by executing the cal instruction. when the cal instruction is executed, 6 bits of immediate data are placed in the six low-order bits of the program counter (pc 5 ?c 0 ), and 0s are placed in the eight high- order bits (pc 13 ?c 6 ). table data addressing mode: a program can branch to an address determined by the contents of four-bit immediate data, the accumulator, and the b register by executing the tbr instruction. p instruction: rom data addressed in table data addressing mode can be referenced with the p instruction as shown in figure 88. if bit 8 of the rom data is 1, the lower eight bits of rom data are written to the accumulator and the b register. if bit 9 is 1, the lower eight bits of rom data are written to the r1 and r2 port output registers. if both bits 8 and 9 are 1, rom data is written to the accumulator and the b register, and also to the r1 and r2 port output registers at the same time. the p instruction has no effect on the program counter. branch destination of a br instruction on a page boundary: when a br instruction is on a page boundary (256n + 255), the program counter will advance to the next page because of the hardware architecture. therefore, when using a br instruction on a page boundary, the branch destination should be set in the next page (see figure 88). hmcs400 series cross assemblers are provided with an automatic paging function that automatically turns the rom page, irrespective of the model.
hd404669 series 116 b 1 b 0 a 3 a 2 a 1 a 0 accumulator referenced rom address address designation ra 9 ra 8 ra 7 ra 6 ra 5 ra 4 ra 3 ra 2 ra 1 ra 0 ra ra ra 10 11 12 13 b 2 b 3 b register 0 0 p 3 p 0 [p] instruction opcode p 2 p 1 ra ro 9 ro 0 ro 8 ro 7 ro 6 ro 5 ro 4 ro 3 ro 2 ro 1 bbbb aa a a 3210 3210 if ro = 1 8 accumulator, b register rom data pattern output ro 9 rom data r2 3 if ro = 1 9 output registers r1, r2 r2 2 r2 1 r2 0 r1 3 r1 2 r1 1 r1 0 ro 0 ro 8 ro 7 ro 6 ro 5 ro 4 ro 3 ro 2 ro 1 figure 87 p instruction br aaa aaa nop 256 (n ?1) + 255 256n br aaa br bbb 256n + 254 256n + 255 256 (n + 1) bbb nop figure 88 branching when the branch destination is on a page boundary
hd404669 series 117 instruction set the mcu has 101 instructions, classified into the following 10 groups: immediate instructions register-to-register instructions ram addressing instructions ram register instructions arithmetic instructions compare instructions ram bit manipulation instructions rom addressing instructions input/output instructions control instructions the functions of these instructions are listed in tables 25 to 34, and an opcode map is shown in table 35. table 25 immediate instructions operation mnemonic operation code function status words/ cycles load a from immediate lai i 100011i 3 i 2 i 1 i 0 i ? a 1/1 load b from immediate lbi i 100000i 3 i 2 i 1 i 0 i ? b 1/1 load memory from immediate lmid i,d 011010i 3 i 2 i 1 i 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 i ? m 2/2 load memory from immediate, increment y lmiiy i 101001i 3 i 2 i 1 i 0 i ? m, y + 1 ? y nz 1/1
hd404669 series 118 table 26 register-register instructions operation mnemonic operation code function status words/ cycles load a from b lab 0001001000 b ? a 1/1 load b from a lba 0011001000 a ? b 1/1 load a from w law 0100000000 0000000000 w ? a 2/2 * load a from y lay 0010101111 y ? a 1/1 load a from spx laspx 0001101000 spx ? a 1/1 load a from spy laspy 0001011000 spy ? a 1/1 load a from mr lamr m 100111m 3 m 2 m 1 m 0 mr (m) ? a 1/1 exchange mr and a xmra m 101111m 3 m 2 m 1 m 0 mr (m) ? a 1/1 note: * the assembler automatically provides an operand for the second word of the law instruction. table 27 ram address instructions operation mnemonic operation code function status words/ cycles load w from immediate lwi i 00111100i 1 i 0 i ? w 1/1 load x from immediate lxi i 100010i 3 i 2 i 1 i 0 i ? x 1/1 load y from immediate lyi i 100001i 3 i 2 i 1 i 0 i ? y 1/1 load w from a lwa 0100010000 0000000000 a ? w 2/2 * load x from a lxa 0011101000 a ? x 1/1 load y from a lya 0011011000 a ? y 1/1 increment y iy 0001011100 y + 1 ? y nz 1/1 decrement y dy 0011011111 y 1 ? y nb 1/1 add a to y ayy 0001010100 y + a ? y ovf 1/1 subtract a from y syy 0011010100 y a ? y nb 1/1 exchange x and spx xspx 0000000001 x ? spx 1/1 exchange y and spy xspy 0000000010 y ? spy 1/1 exchange x and spx, y and spy xspxy 0000000011 x ? spx,y ? spy 1/1 note: * the assembler automatically provides an operand for the second word of the lwa instruction.
hd404669 series 119 table 28 ram register instructions operation mnemonic operation code function status words/ cycles load a from memory lam(xy) 00100100yx m ? a (x ? spx, y ? spy) 1/1 load a from memory lamd d 0110010000 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 m ? a 2/2 load b from memory lbm(xy) 00010000yx m ? b (x ? spx, y ? spy) 1/1 load memory from a lma(xy) 00100101yx a ? m (x ? spx, y ? spy) 1/1 load memory from a lmad d 0110010100 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a ? m 2/2 load memory from a, increment y lmaiy(x) 000101000x a ? m, y + 1 ? y (x ? spx) nz 1/1 load memory from a, decrement y lmady(x) 001101000x a ? m, y ?1 ? y (x ? spx) nb 1/1 exchange memory and a xma(xy) 00100000yx m ? a (x ? spx, y ? spy) 1/1 exchange memory and a xmad d 0110000000 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 m ? a 2/2 exchange memory and b xmb(xy) 00110000yx m ? b (x ? spx, y ? spy) 1/1 note: the meanings of (xy) and (x) are as follows: each instruction marked with (xy) has 4 mnemonics, each with different object codes. for example, different values of x and y of the opcode of the lam(xy) instruction are given below. mnemonic y x function lam 0 0 none lamx 0 1 x ? spx lamy 1 0 y ? spy lamxy 1 1 x ? spx, y ? spy each instruction marked with (x) has 2 mnemonics, each with different object codes. for example, different values of x of the opcode of the lmaiy(x) instruction are given below. mnemonic x function lmaiy 0 none lmaiyx 1 x ? spx
hd404669 series 120 table 29 arithmetic instructions operation mnemonic operation code function status words/ cycles add immediate to a ai i 101000i 3 i 2 i 1 i 0 a + i ? a ovf 1/1 increment b ib 0001001100 b + 1 ? b nz 1/1 decrement b db 0011001111 b 1 ? b nb 1/1 decimal adjust for addition daa 0010100110 1/1 decimal adjust for subtraction das 0010101010 1/1 negate a nega 0001100000 a + 1 ? a 1/1 complement b comb 0101000000 b ? b 1/1 rotate right a with carry rotr 0010100000 1/1 rotate left a with carry rotl 0010100001 1/1 set carry sec 0011101111 1 ? ca 1/1 reset carry rec 0011101100 0 ? ca 1/1 test carry tc 0001101111 ca 1/1 add a to memory am 0000001000 m + a ? a ovf 1/1 add a to memory amd d 0100001000 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 m + a ? a ovf 2/2 add a to memory with carry amc 0000011000 m + a + ca ? a ovf ? ca ovf 1/1 add a to memory with carry amcd d 0100011000 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 m + a + ca ? a ovf ? ca ovf 2/2 subtract a from memory with carry smc 0010011000 m a ca ? a nb ? ca nb 1/1 subtract a from memory with carry smcd d 0110011000 d 9 d 8 d7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 m ?a ? ca ? a nb ? ca nb 2/2 or a and b or 0101000100 a b ? a 1/1 and memory with a anm 0010011100 a ? m ? a nz 1/1 and memory with a anmd d 0110011100 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a ? m ? a nz 2/2 or memory with a orm 0000001100 a m ? a nz 1/1 or memory with a ormd d 0100001100 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a m ? a nz 2/2 eor memory with a eorm 0000011100 a ? m ? a nz 1/1 eor memory with a eormd d 0100011100 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a ? m ? a nz 2/2
hd404669 series 121 table 30 compare instructions operation mnemonic operation code function status words/ cycles immediate not equal to memory inem i 000010i 3 i 2 i 1 i 0 i 1 m nz 1/1 immediate not equal to memory inemd i,d 010010i 3 i 2 i 1 i 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 i 1 m nz 2/2 a not equal to memory anem 0000000100 a 1 m nz 1/1 a not equal to memory anemd d 0100000100 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a 1 m nz 2/2 b not equal to memory bnem 0001000100 b 1 m nz 1/1 y not equal to immediate ynei i 000111i 3 i 2 i 1 i 0 y 1 i nz 1/1 immediate less than or equal to memory ilem i 000011i 3 i 2 i 1 i 0 i m nb 1/1 immediate less than or equal to memory ilemd i,d 010011i 3 i 2 i 1 i 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 i m nb 2/2 a less than or equal to memory alem 0000010100 a m nb 1/1 a less than or equal to memory alemd d 0100010100 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a m nb 2/2 b less than or equal to memory blem 0011000100 b m nb 1/1 a less than or equal to immediate alei i 101011i 3 i 2 i 1 i 0 a i nb 1/1 table 31 ram bit manipulation instructions operation mnemonic operation code function status words/ cycles set memory bit sem n 00100001n 1 n 0 1 ? m (n) 1/1 set memory bit semd n,d 01100001n 1 n 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 ? m (n) 2/2 reset memory bit rem n 00100010n 1 n 0 0 ? m (n) 1/1 reset memory bit remd n,d 01100010n 1 n 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 ? m (n) 2/2 test memory bit tm n 00100011n 1 n 0 m (n) 1/1 test memory bit tm n,d 01100011n 1 n 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 m (n) 2/2
hd404669 series 122 table 32 rom address instructions operation mnemonic operation code function status words/ cycles branch on status 1 br b 1 1 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 1 1/1 long branch on status 1 brl u 010111p 3 p 2 p 1 p 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 2/2 long jump unconditionally jmpl u 010101p 3 p 2 p 1 p 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 2/2 subroutine jump on status 1 cal a 0111a 5 a 4 a 3 a 2 a 1 a 0 1 1/2 long subroutine jump on status 1 call u 010110p 3 p 2 p 1 p 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 2/2 table branch tbr p 001011p 3 p 2 p 1 p 0 1 1/1 return from subroutine rtn 0000010000 1/3 return from interrupt rtni 0000010001 1 ? ie, carry restored st 1/3 table 33 input/output instructions operation mnemonic operation code function status words/ cycles set discrete i/o latch sed 0011100100 1 ? d (y) 1/1 set discrete i/o latch direct sedd m 101110m 3 m 2 m 1 m 0 1 ? d (m) 1/1 reset discrete i/o latch red 0001100100 0 ? d (y) 1/1 reset discrete i/o latch direct redd m 100110m 3 m 2 m 1 m 0 0 ? d (m) 1/1 test discrete i/o latch td 0011100000 d (y) 1/1 test discrete i/o latch direct tdd m 101010m 3 m 2 m 1 m 0 d (m) 1/1 load a from r-port register lar m 100101m 3 m 2 m 1 m 0 r (m) ? a 1/1 load b from r-port register lbr m 100100m 3 m 2 m 1 m 0 r (m) ? b 1/1 load r-port register from a lra m 101101m 3 m 2 m 1 m 0 a ? r (m) 1/1 load r-port register from b lrb m 101100m 3 m 2 m 1 m 0 b ? r (m) 1/1 pattern generation p p 011011p 3 p 2 p 1 p 0 1/2
hd404669 series 123 table 34 control instructions operation mnemonic operation code function status words/ cycles no operation nop 0000000000 1/1 start serial sts 0101001000 1/1 standby mode/watch mode * sby 0101001100 1/1 stop mode/watch mode stop 0101001101 1/1 note: * only after a transition from subactive mode.
hd404669 series 124 table 35 opcode map r8 l h r9 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f lbi i(4) lyi i(4) lxi i(4) lai i(4) lbr m(4) lar m(4) redd m(4) lamr m(4) ai i(4) lmiiy i(4) tdd m(4) alei i(4) lrb m(4) lra m(4) sedd m(4) xmra m(4) 0 0 1 1-word/2-cycle instruction 1-word/3-cycle instruction ram direct address instruction (2-word/2-cycle) 2-word/2-cycle instruction 0123456789abcdef nop xspx xspy xspxy anem am orm lbm(xy) bnem lab ib lmaiy(x) ayy laspy iy rtn rtni alem amc eorm nega red laspx tc inem i(4) ilem i(4) ynei i(4) xma(xy) lam(xy) sem n(2) lma(xy) rem n(2) smc tm n(2) anm rotr daa das lay rotl db dy sec lba lya rec lxa blem syy sed xmb(xy) lmady(x) td lwi i(2) tbr p(4)
hd404669 series 125 r8 l h r9 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f 1 0 1 1-word/2-cycle instruction 1-word/3-cycle instruction ram direct address instruction (2-word/2-cycle) 2-word/2-cycle instruction 0123456789abcdef law anemd amd ormd lwa alemd amcd eormd comb or sts sby stop inemd i(4) ilemd i(4) jmpl p(4) call p(4) brl p(4) xmad lamd semd n(2) lmad remd n(2) smcd tmd n(2) anmd lmid i(4) cal a(6) br b(8) p p(4)
hd404669 series 126 absolute maximum ratings item symbol value unit notes supply voltage v cc ?.3 to +7.0 v programming voltage v pp ?.3 to +14.0 v 1 pin voltage v t ?.3 to (v cc + 0.3) v total permissible input current (to chip) ? i o 100 ma 2 total permissible output current (from chip) e ? i o 50 ma 3 maximum input current (to chip) i o 4 ma 4, 5 30 ma 4, 6 maximum output current (from chip) ei o 4 ma 7, 8 20 ma 7, 9 operating temperature t opr e20 to +75 c10 storage temperature t stg e55 to +125 c11 notes: 1. applies to d 13 (v pp ) of the hd407a4669. 2. the total permissible input current is the total of input currents simultaneously flowing in from all the i/o pins to ground. 3. the total permissible output current is the total of output currents simultaneously flowing out from v cc to all i/o pins. 4. the maximum input current is the maximum current flowing from each i/o pin to ground. 5. applies to d 0 ed 3, r0er4 and r6era. 6. applies to d 4 , d 5 and d 9 ed 11 7. the maximum output current is the maximum current flowing out from v cc to each i/o pin. 8. applies to d 4 , d 5 , d 9 ed 11 , r0er4 and r6era. 9. applies to d 0 ed 3 . 10. the operating temperature indicates the temperature range in which power can be supplied to the lsi (voltage v cc shown in the electrical characteristics tables can be applied). 11. in the case of chips, the storage specification differs from that of the package products. please consult your hitachi sales representative for details. permanent damage may occur if these absolute maximum ratings are exceeded. normal operation must be under the conditions stated in the electrical characteristics tables. if these conditions are exceeded, the lsi may malfunction or its reliability may be affected.
hd404669 series 127 electrical characteristics dc characteristics (hd404668, hd4046612, hd404669, hd40a4668, HD40A46612, hd40a4669: v cc = 1.8 to 5.5 v, gnd = 0 v, t a = e20 c to +75 c; hcd404669: v cc = 1.8 to 5.5 v, gnd = 0 v, t a = +75 c; hd407a4669: v cc = 2.2 to 5.5 v, gnd = 0 v, t a = e20 c to +75 c, unless otherwise specified) item symbol pin(s) min typ max unit test condition notes input high voltage v ih reset, sck 1 , si 1 , int 0 , int 1 , int 2 , int 3 , int 4 , stopc , evnd 0.9v cc ?v cc + 0.3 v ? osc 1 v cc e 0.3 ? v cc + 0.3 v external clock operation input low voltage v il reset, sck 1 , si 1 , int 0 , int 1 , int 2 , int 3 , int 4 , stopc , evnd e0.3 ? 0.10v cc v? osc 1 e0.3 ? 0.3 v external clock operation output high voltage v oh sck 1 , so 1 , toc, tod v cc e 0.5 ? ? v ei oh = 0.3 ma output low voltage v ol sck 1 , so 1 , toc, tod ? ? 0.4 v i ol = 0.4 ma i/o leakage current ? i i l ? reset, sck 1 , si 1 , int 0 , int 1 , int 2 , int 3 , int 4 , stopc , evnd, osc 1 , so 1 , toc, tod ? ? 1.0 m av in = 0 v to v cc 1 active mode current dissipation (digital input mode) i cc1 v cc ? 2.5 5.0 ma v cc = 5.0 v, f osc = 4 mhz 2 i cc2 v cc ? 0.3 1.0 ma v cc = 3.0 v, f osc = 800 khz 2 i cc3 v cc ? 5.0 9.0 ma hd40a4668, HD40A46612, hd40a4669, hd407a4669: v cc = 5 v, f osc = 8 mhz 2
hd404669 series 128 item symbol pin(s) min typ max unit test condition notes active mode current dissipation (analog compare mode) i cmp1 v cc 6.5 9.0 ma v cc = 5v, f osc = 4mhz 3 i cmp2 v cc 2.8 3.5 ma v cc = 3v, f osc = 800khz 3 i cmp3 v cc 9.0 13.0 ma hd40a4668, HD40A46612, hd40a4669, hd407a4669: v cc = 5v, f osc = 8mhz 3 standby mode current dissipation i sby1 v cc 1.0 2.0 ma v cc = 5v, f osc = 4mhz 4 i sby2 v cc 0.1 0.3 ma v cc = 3v, f osc = 800khz 4 i sby3 v cc 2.0 4.0 ma hd40a4668, HD40A46612, hd40a4669, hd407a4669: v cc = 5v, f osc = 8mhz 4 subactive mode current dissipation i sub v cc ?835 m av cc = 3 v, 32 khz oscillator used 5 watch mode current dissipation i wtc v cc ? 4 7.5 m av cc = 3 v, 32 khz oscillator used 5 stop mode current dissipation i stop v cc ? 0.5 5 m av cc = 3 v, no 32 khz oscillator 5 stop mode retention voltage v stop v cc 1.5 ? ? v no 32 khz oscillator 6 comparator input reference voltage range vc ref vc ref 0?v cc ?1.2 v notes: 1. output buffer current is excluded. 2. power supply current when the mcu is in the reset state and there are no i/o currents. test conditions: mcu: reset pins: reset at v cc (v cc e 0.3 v to v cc ) test at v cc (v cc e 0.3 v to v cc ) 3. power supply current when pins rd 0 and rd 1 are in analog input mode and there are no i/o currents. test conditions: mcu: dtmf not operating pins: rd 0 /comp 0 : at gnd (0 v to 0.3 v) rd 1 /comp 1 : at gnd (0 v to 0.3 v) re 0 /vc ref : at gnd (0 v to 0.3 v)
hd404669 series 129 4. power supply current when the on-chip timers are operating and there are no i/o currents. test conditions: mcu: i/o reset serial interface stopped dtmf not operating standby mode pins: reset at gnd (0 v to 0.3 v) test at v cc (v cc e 0.3 v to v cc ) 5. these are the source currents when no i/o current is flowing. test conditions: pins: reset at gnd (0 v to 0.3 v) test at v cc (v cc e 0.3 v to v cc ) d 13 at v cc (v cc e 0.3 v to v cc ) for the hd407a4669 6. the required voltage for ram data retention.
hd404669 series 130 i/o characteristics for standard pins (hd404668, hd4046612, hd404669, hd40a4668, HD40A46612, hd40a4669: v cc = 1.8 to 5.5 v, gnd = 0 v, t a = e20 c to +75 c; hcd404669: v cc = 1.8 to 5.5 v, gnd = 0 v, t a = +75 c; hd407a4669: v cc = 2.2 to 5.5 v, gnd = 0 v, t a = e20 c to +75 c, unless otherwise specified) item symbol pin(s) min typ max unit test condition notes input high voltage v ih d 12 , d 13 , r0 to r4, r6 to ra, rd, re 0 0.7v cc ? cc + 0.3 v input low voltage v il d 12 , d 13 , r0 to r4, r6 to ra, rd, re 0 ?.3 0.3v cc v output high voltage v oh r0 to r4, r6 to ra v cc ?0.5 v i oh = 0.3 ma output low voltage v ol r0 to r4, r6 to ra 0.4 v i ol = 0.4 ma i/o leakage current ? i i l ? d 12 , r0 to r4, r6 to ra, rd, re 0 ??1 m av in = 0 v to v cc 1 d 13 ??1 m a hd404668, hd4046612, hd404669, hcd404669, hd40a4668, HD40A46612, hd40a4669: v in = 0v to v cc 1 ??1 m a hd407a4669: v in = v cc e 0.3v to v cc 1 ??20 m a hd407a4669: v in = 0v to 0.3v 1 pull-up mos current ei pu r0 to r4, r6 to ra 10 50 150 m av cc = 3.0 v, v in = 0 v input high voltage v iha comp 0 , comp 1 vc ref +0.1 ? ? v analog compare mode input low voltage v ila comp 0 , comp 1 ?? vc ref e 0.1 v analog compare mode note: 1. output buffer current is excluded.
hd404669 series 131 i/o characteristics for high-current (hd404668, hd4046612, hd404669, hd40a4668, HD40A46612, hd40a4669: v cc = 1.8 to 5.5 v, gnd = 0 v, t a = e20 c to +75 c; hcd404669: v cc = 1.8 to 5.5 v, gnd = 0 v, t a = +75 c; hd407a4669: v cc = 2.2 to 5.5 v, gnd = 0 v, t a = e20 c to +75 c, unless otherwise specified) item symbol pin(s) min typ max unit test condition notes input high voltage v ih d 0 to d 5 , d 9 to d 11 0.7v cc ? cc + 0.3 v input low voltage v il d 0 to d 5 , d 9 to d 11 ?.3 0.3v cc v output high voltage v oh d 0 to d 5 , d 9 to d 11 v cc ?0.5 v i oh = 0.3 ma d 0 to d 3 v cc ?2.0 v i oh = 10 ma v cc = 4.5v to 5.5v output low voltage v ol d 0 to d 5 , d 9 to d 11 0.4 v i ol = 0.4 ma d 4 , d 5 , d 9 to d 11 2.0 v i ol = 15 ma, v cc = 4.5 v to 5.5 v i/o leakage current ? i i l ? d 0 to d 5 , d 9 to d 11 ??1 m av in = 0 v to v cc 1 pull-up mos current ei pu d 4 , d 5 , d 9 to d 11 10 50 150 m av cc = 3 v, v in = 0 v pull-down mos current i pd d 0 to d 3 10 50 150 m av cc = 3 v, v in = 3 v note: 1. output buffer current is excluded.
hd404669 series 132 dtmf characteristics (hd404668, hd4046612, hd404669, hd40a4668, HD40A46612, hd40a4669: v cc = 1.8 to 5.5 v, gnd = 0 v, t a = e20 c to +75 c; hcd404669: v cc = 1.8 to 5.5 v, gnd = 0 v, t a = +75 c; hd407a4669: v cc = 2.2 to 5.5 v, gnd = 0 v, t a = e20 c to +75 c, unless otherwise specified) item symbol pin min typ max unit test condition notes tone output voltage (1) v or toner 500 660 mv r ms vt ref ?gnd = 2.0 v, r l = 100 k w, v cc = 2.2 to 5.0v 1 tone output voltage (2) v oc tonec 520 690 ? mv r ms vt ref e gnd = 2.0 v, r l = 100 k w, v cc = 2.2 to 5.0v 1 tone output distortion %dis ? ? 3 7 % short circuit between toner and tonec, r l = 100 k w 2 tone output ratio db cr ? ? 2.5 ? db short circuit between toner and tonec, r l = 100 k w 2 notes: these characteristics are guaranteed with an operating frequency, f osc , of 400 khz, 800 khz, 2 mhz, 3.58 mhz, 4 mhz, 7.16 mhz, or 8 mhz. 1. see figure 89. 2. see figure 90.
hd404669 series 133 ac characteristics (hd404668, hd4046612, hd404669, hd40a4668, HD40A46612, hd40a4669: v cc = 1.8 to 5.5 v, gnd = 0 v, t a = e20 c to +75 c; hcd404669: v cc = 1.8 to 5.5 v, gnd = 0 v, t a = +75 c; hd407a4669: v cc = 2.2 to 5.5 v, gnd = 0 v, t a = e20 c to +75 c, unless otherwise specified) item symbol pin(s) min typ max unit test condition notes clock oscillation frequency f osc osc 1 , osc 2 400 khz 1 800 khz 1 2 mhz 1 3.58 mhz 1 4 mhz 1 7.16 mhz hd40a4668, HD40A46612, hd40a4669, hd407a4669: v cc = 4.0v to 5.5v 1 8 mhz x1, x2 32.768 khz instruction cycle time t cyc 8 m sf osc = 4 mhz, division by 32 2 ?4 ? m sf osc = 4 mhz, division by 16 2 ?2 ? m sf osc = 4 mhz, division by 8 2 ?1 ? m sf osc = 4 mhz, division by 4 2 t subcyc ? ? 244.14 ? m s 32 khz oscillator used, division by 8 3 ? 122.07 ? m s 32 khz oscillator used, division by 4 3 oscillation stabilization time (ceramic oscillator) t rc osc 1 , osc 2 ? ? 7.5 ms 4, 5 oscillation stabilization time (crystal oscillator) t rc osc 1 , osc 2 ? ? 30 ms 4, 5, 12 x1, x2 ? ? 2 s t a = e10 c to +60 c 4 external clock high width t cph osc 1 1100 ? ? ns f osc = 400 khz 6 550 ? ? ns f osc = 800 khz 215 ? ? ns f osc = 2 mhz 115 ? ? ns f osc = 3.58 mhz 105 ? ? ns f osc = 4 mhz 57.5 ? ? ns f osc = 7.16 mhz 6, 11 52.5 ? ? ns f osc = 8 mhz
hd404669 series 134 item symbol pin(s) min typ max unit test condition notes external clock low width t cpl osc 1 1100 ns f osc = 400 khz 6 550 ns f osc = 800 khz 215 ns f osc = 2 mhz 115 ns f osc = 3.58 mhz 105 ns f osc = 4 mhz 57.5 ns f osc = 7.16 mhz 6, 11 52.5 ns f osc = 8 mhz external clock rise time t cpr osc 1 150 ns f osc = 400 khz 6 75 ns f osc = 800 khz 35 ns f osc = 2 mhz 25 ns f osc = 3.58 mhz 20 ns f osc = 4 mhz 12.5 ns f osc = 7.16 mhz 6, 11 10 ns f osc = 8 mhz external clock fall time t cpf osc 1 150 ns f osc = 400 khz 6 75 ns f osc = 800 khz 35 ns f osc = 2 mhz 25 ns f osc = 3.58 mhz 20 ns f osc = 4 mhz 12.5 ns f osc = 7.16 mhz 6, 11 10 ns f osc = 8 mhz int 0 eint 4 , evnd high widths t i h int 0 to int 4 , evnd 2?? t cyc / t subcyc ?7 int 0 eint 4 , evnd low widths t i l int 0 to int 4 , evnd 2?? t cyc / t subcyc ?7 reset high width t rsth reset 2 ? ? t cyc ?8 stopc low width t stpl stopc 1??t rc ?9 reset fall time t rstf reset ? ? 20 ms ? 8 stopc rise time t stpr stopc ? ? 20 ms ? 9 input capacitance c in all pins except d 13 ? ? 15 pf f = 1 mhz v in = 0 v, d 13 ? ? 15 pf hd40a4668, HD40A46612, hd40a4669, hcd404669, hd404668, hd4046612, hd404669: f = 1mhz, v in = 0v ? ? 40 pf hd407a4669: f = 1mhz, v in = 0v
hd404669 series 135 item symbol pin(s) min typ max unit test condition notes analog comparator stabilization time t cstb comp 0 to comp 1 2t cyc v cc = 2.2 v to 5.5v 10 10 t cyc v cc = 1.8 v to less than 2.2v notes: 1. set bits 0 and 1 (ssr10, ssr11) of system clock select register 1 (ssr1: $029) and bits 2 and 3 (ssr22, ssr23) of system clock select register 2 (ssr2: $02a) according to the system clock frequency used. 2. set bits 0 and 1 (ssr20, ssr21) of system clock select register 2 (ssr2: $02a) according to the system clock frequency division ratio used. 3. set bit 2 (ssr12) of system clock select register 1 (ssr1: $029) according to the subsystem clock frequency division ratio used. 4. the oscillation stabilization time is defined as follows: (1) the time required for the oscillation to settle after v cc has reached the minimum specification value at power-on. (2) the time required for the oscillation to settle after reset input has gone high when stop mode is cleared. (3) the time required for the oscillation to settle after stopc input has gone low when stop mode is cleared. to ensure enough time for the oscillation to settle at power-on or when stop mode is cleared, input the reset or stopc signal for at least time t rc . the oscillation stabilization time will depend on the circuit constants and stray capacitance. the oscillator should be determined in consultation with the oscillator manufacturer. 5. set bits 0 and 1 (mis0, mis1) in the miscellaneous register (mis: $00c) according to the oscillation stabilization time of the system oscillator. 6. see figure 91. 7. see figure 92. unit t cyc applies when the mcu is in standby mode or active mode. unit t subcyc applies when the mcu is in watch mode or subactive mode. 8. see figure 93. 9. see figure 94. 10. this is the time required for the analog comparator to settle, ensuring that the correct data is read, after pins rd 0 /comp 0 and rd 1 /comp 1 are set to analog input mode. 11. applies to the hd40a4668, HD40A46612, hd40a4669, and hd407a4669. the test condition is v cc = 4.0 to 5.5 v. 12. applies to the hd404668, hd4046612, hd404669, hcd404669, hd40a4668, HD40A46612, and hd40a4669. the test condition is v cc = 2.0 to 5.5 v.
hd404669 series 136 serial interface timing characteristics (hd404668, hd4046612, hd404669, hd40a4668, HD40A46612, hd40a4669: v cc = 1.8 to 5.5 v, gnd = 0 v, t a = e20 c to +75 c; hcd404669: v cc = 1.8 to 5.5 v, gnd = 0 v, t a = +75 c; hd407a4669: v cc = 2.2 to 5.5 v, gnd = 0 v, t a = e20 c to +75 c, unless otherwise specified) during transmit clock output item symbol pin min typ max unit test condition notes transmit clock cycle time t scyc sck 1 1.0 ? ? t cyc load shown in figure 96 1 transmit clock high width t sckh sck 1 0.4 ? ? t scyc load shown in figure 96 1 transmit clock low width t sckl sck 1 0.4 ? ? t scyc load shown in figure 96 1 transmit clock rise time t sckr sck 1 ? ? 100 ns load shown in figure 96 1 transmit clock fall time t sckf sck 1 ? ? 100 ns load shown in figure 96 1 serial output data delay time t dso so 1 ? ? 300 ns load shown in figure 96 1 serial input data setup time t ssi si 1 200 ? ? ns ? 1 serial input data hold time t hsi si 1 200 ? ? ns ? 1 note: 1. refer to figure 95. during transmit clock input item symbol pin min typ max unit test condition notes transmit clock cycle time t scyc sck 1 1.0 ? ? t cyc ?1 transmit clock high width t sckh sck 1 0.4 ? ? t scyc ?1 transmit clock low width t sckl sck 1 0.4 ? ? t scyc ?1 transmit clock rise time t sckr sck 1 ? ? 100 ns ? 1 transmit clock fall time t sckf sck 1 ? ? 100 ns ? 1 serial output data delay time t dso so 1 ? ? 300 ns load shown in figure 96 1 serial input data setup time t ssi si 1 200 ? ? ns ? 1 serial input data hold time t hsi si 1 200 ? ? ns ? 1 note: 1. refer to figure 95.
hd404669 series 137 tonec toner r l = 100 k w gnd r l = 100 k w figure 89 tone output load circuit tonec toner r l = 100 k w gnd figure 90 distortion and db cr load circuit 1/f cp t cpl t cpf t cpr t cph v cc ? 0.3 v 0.3 v osc 1 figure 91 external clock timing t il t ih 0.9 v cc 0.1 v cc int 0 to int 4 , evnd figure 92 interrupt timing
hd404669 series 138 t rsth 0.9 v cc 0.1 v cc t rstf reset figure 93 reset timing t stpl 0.9 v cc 0.1 v cc stopc t stpr figure 94 stopc timing t scyc t sckf t sckl t sckh t dso t ssi t hsi 0.9 v cc 0.1v cc v cc ?0.5 v 0.4 v v cc ?0.5 v (0.9 v cc ) * 0.4 v (0.1 v cc ) * si 1 so 1 sck 1 note: * v cc ?0.5 v and 0.4 v are the threshold voltages during serial clock output. 0.9 v cc and 0.1 v cc are the threshold voltages during serial clock input. t sckr figure 95 serial interface timing
hd404669 series 139 v cc r l = 2.6 k w 1s2074 h or equivalent r = 12 k w c = 30 pf test point figure 96 timing load circuit
hd404669 series 140 notes on rom out please note the following when ordering hd404668, hd4046612, hd40a4668, or HD40A46612 rom. on rom out, fill the rom area indicated below with 1s to create the same data size as a 16-kword version (hd404669, hd40a4669). a 16-kword data size is required to change rom data to mask manufacturing data since the program used is for a 16-kword version. this limitation applies when using an eprom or a data base. $0000 $000f $0010 $003f $0040 $1fff $2000 $3fff 8-kword rom versions: hd404668, hd40a4668 write all-1 data to addresses $2000 to $3fff. vector addresses zero page subroutine area (64 words) program and pattern area (8,192 words) $0000 $000f $0010 $003f $0040 $2fff $3000 $3fff 12-kword rom versions: hd4046612, HD40A46612 write all-1 data to addresses $3000 to $3fff. vector addresses zero page subroutine area (64 words) program and pattern area (12,288 words) not used note: write all-1 data in shaded areas. not used
hd404669 series 141 hd404668/hd4046612/hd404669/hcd404669/hd40a4668/HD40A46612/hd40a4669 option list please check off the appropriate applications and enter the necessary information. date of order / / customer department name rom code name lsi number (hitachi entry) 1. rom size standard operation version: hd404668 8-kword high-speed operation version: hd40a4668 standard operation version: hd4046612 12-kword high-speed operation version: HD40A46612 standard operation version: hd404669 16-kword high-speed operation version: hd40a4669 chip version: hcd404669 2. optional functions * with 32-khz cpu operation, with time-base for clock * without 32-khz cpu operation, with time-base for clock without 32-khz cpu operation, without time-base for clock note: * options marked with an asterisk require a subsystem crystal oscillator (x1, x2). 3. rom code data type please specify the first type below (the upper bits and lower bits are mixed together), when using the eprom on-package microcomputer type (including ztat tm version). the upper bits and lower bits are mixed together. the upper five bits and lower five bits are programmed to the same eprom in alternating order (i.e., lululu...). the upper bits and lower bits are separated. the upper five bits and lower five bits are programmed to different eproms 4. system oscillator (osc 1 and osc 2 ) ceramic oscillator f = mhz crystal oscillator f = mhz external clock f = mhz 5. stop mode 6. package used fp-64a not used chip note: the specifications of shipped chips differ from of the package product. please contact our sales staff for details.
hd404669 series 142 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:

▲Up To Search▲

Price & Availability of HD40A46612

	To Download HD40A46612 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .